Hi Brad I only had time work on the FPGA interface to the DDR3 DRAM... for our application the CPU interface was more of a nice to have. The only other person that I know of who might have done some work on this is Rurik?
MIG (Memory Interface Generator) is a Xilinx tool that allows you to generate the memory controller VHDL/Verilog code for various memory modules. Cheers, JP On Fri, Feb 13, 2015 at 5:44 AM, Brad Dober <[email protected]> wrote: > Hi Casperites, > > Has anyone implemented the DDR3 DRAM on ROACH2 with a PPC interface? > I saw some whispers of work on a DRAM yellow block for ROACH2 by Juan > Pierre in 2013 on the mail archive, but I don't think there was ever a PPC > interface ever built. (Some mention of a MIG was made, but I'm not sure > what that is.) > > Thanks for the help! > > Brad Dober > Ph.D. Candidate > Department of Physics and Astronomy > University of Pennsylvania > Cell: 262-949-4668 >
