Hi Brad, Myself and Rurik Primiani did some work on the PPC interface to the DDR3 module over a year ago, but had to stop before completion. I think I have some files around in github in the ddr3-devel branch of the sma-wideband repo, but it is in a state where I was not getting error-free reads (I think .03% of data was incorrect) and was contemplating starting fresh. In the interest of time we adapted our model to use only the FPGA interface for reads and writes.
Happy to speak more if you want to pick this up. --Laura On Fri, Feb 13, 2015 at 12:29 AM, Juan-Pierre Jansen van Rensburg < [email protected]> wrote: > Hi Brad > > I only had time work on the FPGA interface to the DDR3 DRAM... for our > application the CPU interface was more of a nice to have. > The only other person that I know of who might have done some work on this > is Rurik? > > MIG (Memory Interface Generator) is a Xilinx tool that allows you to > generate the memory controller VHDL/Verilog code for various memory > modules. > > Cheers, > JP > > On Fri, Feb 13, 2015 at 5:44 AM, Brad Dober <[email protected]> wrote: > >> Hi Casperites, >> >> Has anyone implemented the DDR3 DRAM on ROACH2 with a PPC interface? >> I saw some whispers of work on a DRAM yellow block for ROACH2 by Juan >> Pierre in 2013 on the mail archive, but I don't think there was ever a PPC >> interface ever built. (Some mention of a MIG was made, but I'm not sure >> what that is.) >> >> Thanks for the help! >> >> Brad Dober >> Ph.D. Candidate >> Department of Physics and Astronomy >> University of Pennsylvania >> Cell: 262-949-4668 >> > >
