Nishanth at ASU has been working on getting the MKID ADC/DAC working on the ROACH2.
The DAC is fully functional, and the ADC works up to CLK frequency of 480 MHz, then some NCO clock errors pop up. We are also interested in the PPC interface to the DRAM. Feel free to contact Nishanth and I to talk about this further. Brad Dober Ph.D. Candidate Department of Physics and Astronomy University of Pennsylvania Cell: 262-949-4668 On Fri, Mar 6, 2015 at 2:56 AM, Wesley New <[email protected]> wrote: > Hi Johnathan. > > I can point you in the right direction for the first issue you are having. > It seems that no one has used that ADC on a ROACH2 before so you will need > to migrate the core to support Virtex 6. This is probably just a > replacement of the DCM with and MMCM, but there may be other issues. > > You will need to edit this file: > > > https://github.com/casper-astro/mlib_devel/blob/master/xps_base/XPS_ROACH2_base/pcores/adc_mkid_interface_v1_00_a/hdl/vhdl/adc_mkid_interface.vhd > > The DCM is at the end of the file. > > You can see how the MMCM has been setup in the MKADC here: > > > https://github.com/casper-astro/mlib_devel/blob/master/xps_base/XPS_ROACH2_base/pcores/mkadc_interface_v1_00_a/hdl/vhdl/adc5g_dmux1_interface.vhd > > For more info on the MMCM see the Xilinx Clocking Resource users guide. > > Regards > > Wesley > > > Wesley New > South African SKA Project > +2721 506 7300 > www.ska.ac.za > > > > On Fri, Mar 6, 2015 at 2:54 AM, Gard, Johnathon D. < > [email protected]> wrote: > >> Hello Everyone, >> >> I have a series of questions concerning the ROACH2 system and tool flow. >> >> OS = Ubuntu 14.04.2 LTS >> >> Tool flow = ISE 14.7, MATLAB R2012b, mlib-devel-master (casper-astro git >> clone) >> >> Hardware = MUSIC ADC/DAC board and MUSIC IF_Board from Techne Instruments >> (Rich Raffanti) >> >> >> >> >> >> First thing, syncing the FPGA clock to the ADC/DAC clock. Using the mkid >> adc or dac blocks from the xps library and selecting any one of the >> adc0_clk, adc1_clk, dac0_clk, or dac1_clk settings in the xsg_core_config >> results in errors in the compilation. There are usually one of two errors >> the come up “Cannot retarget DCM to MMCM” because of VCO frequencies being >> out of range or an input period of 0.00ns for the DCM. Looking at the >> Xilinx forums, they generally do not recommend letting the toolflow upgrade >> the DCM to a MMCM. There are a lot of complications that arise from this. I >> was wondering if anyone has a block set were they have already fixed this >> problem and have been able to use an external clock from the ZDOK >> connectors. >> >> >> >> I, at one point, found an email on the CASPER archive about this same >> problem and downloaded the attached block set. However this did not work >> either. I really wish I could find this email again. >> >> >> >> Another question I had was about the DDR3 DRAM. >> >> >> >> http://www.mail-archive.com/casper%40lists.berkeley.edu/msg04323.html >> >> >> >> I was if anyone has tried to change the IDELAYCTRL frequency so that the >> RAM can run at a higher clock speed. This work may be able to be tied into >> the PPC interface work or error free work from the following email. >> >> >> >> http://www.mail-archive.com/casper%40lists.berkeley.edu/msg05670.html >> >> >> >> I would be more than happy to try and help with this. I have an interest >> in the PPC interface but error free operation is more critical. >> >> >> >> Johnathon Gard >> >> National Institute of Standards and Technology >> >> Quantum Sensors Project >> >> >> >
