Hey Dave This should have been fixed in commit b1295df1ef.
Cheers Andrew On Wed, Apr 1, 2015 at 10:31 AM, David MacMahon <[email protected]> wrote: > Hi, Jason, > > On Mar 31, 2015, at 11:25 PM, Jason Manley wrote: > > > Yes, there is a simulation model included in the Simulink space for that. > > Yes, I know there is a simulation model included, but does it work? > > It looks like the "qdr_sim_model" passes the "data_in" signal through a > Gateway In block ("sim_data_in") that outputs a 36 bit wide signal. This > 36-bit data path propagate out of "qdr_sim_model" and then through another > Gateway In block ("<BLOCK_NAME>_data_out") that outputs a 72 bit wide > signal. > > How could that ever work? > > > I don't believe we've ever tried co-simulating the underlying VHDL from > Simulink, if that's what you mean. > > No, that's not what I mean. That would require a bus functional model of > the QDR chip and I don't think that exists in the repository. > > Thanks, > Dave > > >
