Hi all, ! New year Greetings !
I Installed MATLAB2012b and ISE 14.6 on UBUNTU14.04 64 bit version. Firstly I am trying to compile a simple model to begin with .There was some issues to begin with and I solved it with the solutions available in the forum.
https://www.mail-archive.com/[email protected]/msg01913.html Later I am trying to compile this design I was getting this error. system log and matlab command prompt also attached here with. -- Thanks and regards ______________________ Indrajit Vittal Barve Engineer, Radio Astronomy Group, Indian Institute of Astrophysics, Gauribidanur. Pin : 561210 Mobile : +91-9845432754. Office : +91-8155291655.
test2sysgrn.slx
Description: Binary data
Saved contents of this file to system_log.14.5 during revup to EDK 14.6. ===================== Opened log file ===================== ===================== Opened log file ===================== Xilinx Platform Studio (XPS) Xilinx EDK 14.6 Build EDK_P.68d Xilinx EDK 14.6 Build EDK_P.68d Overriding IP level properties ... Computing clock values... INFO:EDK - Cannot determine the input clock associated with port : infrastructure_inst:epb_clk. Clock DRCs will not be performed on this core and cores connected to it. INFO:EDK - Cannot determine the input clock associated with port : infrastructure_inst:epb_clk. Clock DRCs will not be performed on this core and cores connected to it. INFO:EDK - Cannot determine the input clock associated with port : infrastructure_inst:epb_clk. Clock DRCs will not be performed on this core and cores connected to it. INFO:EDK - Cannot determine the input clock associated with port : infrastructure_inst:epb_clk. Clock DRCs will not be performed on this core and cores connected to it. INFO:EDK - Cannot determine the input clock associated with port : infrastructure_inst:epb_clk. Clock DRCs will not be performed on this core and cores connected to it. Performing IP level DRCs on properties... Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC... Address Map for Processor epb_opb_bridge_inst (0000000000-0x0000ffff) sys_block_inst opb0 (0x01000000-0x010000ff) test2sysgrn_period opb0 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++++++++++++++++++++ WARNING !!! +++++++++++++++++++++++++++++ ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ WARNING:EDK - Processor epb_opb_bridge_inst has no memory mapped at its reset vector. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ INFO:EDK - IPNAME: opb_v20, INSTANCE:opb0 - tool is overriding PARAMETER C_NUM_MASTERS value to 1 - /home/indrajit/ROACH_programs/test2sysgrn/XPS_ROACH_base/pcores/opb_v20_v1_10 _c/data/opb_v20_v2_1_0.mpd line 74 INFO:EDK - IPNAME: opb_v20, INSTANCE:opb0 - tool is overriding PARAMETER C_NUM_SLAVES value to 2 - /home/indrajit/ROACH_programs/test2sysgrn/XPS_ROACH_base/pcores/opb_v20_v1_10 _c/data/opb_v20_v2_1_0.mpd line 75 Checking platform address map ... XPS% Evaluating file run_xps.tcl ERROR:EDK - Error while running "gmake -f system.make bits".
>> casper_xps
Detected Linux OSError using gen_xps_files (line 95)
Block names may not have spaces - test2sysgrn/XSG core config
Detected Linux OS#############################
## System Update ##
#############################
Warning: The model 'test2sysgrn' does not have continuous states, hence
Simulink is using the
solver 'VariableStepDiscrete' instead of solver 'ode45'. You can disable this
diagnostic by
explicitly specifying a discrete solver in the solver tab of the Configuration
Parameters
dialog, or by setting the 'Automatic solver parameter selection' diagnostic to
'none' in the
Diagnostics tab of the Configuration Parameters dialog
> In gen_xps_files at 202
In casper_xps>run_Callback at 155
In casper_xps at 88
In
@(hObject,eventdata)casper_xps('run_Callback',hObject,eventdata,guidata(hObject))
#############################
## Block objects creation ##
#############################
######################
## Checking objects ##
######################
Running system generator ...
Warning: The model 'test2sysgrn' does not have continuous states, hence
Simulink is using
the solver 'VariableStepDiscrete' instead of solver 'ode45'. You can disable
this
diagnostic by explicitly specifying a discrete solver in the solver tab of the
Configuration Parameters dialog, or by setting the 'Automatic solver parameter
selection'
diagnostic to 'none' in the Diagnostics tab of the Configuration Parameters
dialog
> In
> /opt/Xilinx/14.6/ISE_DS/ISE/sysgen/bin/lin64/xlCompileGenerateMdl.p>xlCompileGenerateMdl
> at 203
In
/opt/Xilinx/14.6/ISE_DS/ISE/sysgen/bin/lin64/xlGenerateButton.p>xlGenerateButton
at 302
In gen_xps_files at 322
In casper_xps>run_Callback at 155
In casper_xps at 88
In
@(hObject,eventdata)casper_xps('run_Callback',hObject,eventdata,guidata(hObject))
Warning: Possible deprecated use of get on a Java object with an HG Property
'UserData'.
> In xlNGCPostGeneration at 57
In
/opt/Xilinx/14.6/ISE_DS/ISE/sysgen/bin/lin64/xlruntargetfcn.p>xlruntargetfcn at
12
In
/opt/Xilinx/14.6/ISE_DS/ISE/sysgen/bin/lin64/xlGenerateButton.p>xlGenerateButton
at 478
In gen_xps_files at 322
In casper_xps>run_Callback at 155
In casper_xps at 88
In
@(hObject,eventdata)casper_xps('run_Callback',hObject,eventdata,guidata(hObject))
Warning: Possible deprecated use of set on a Java object with an HG Property
'UserData'.
> In xlNGCPostGeneration at 60
In
/opt/Xilinx/14.6/ISE_DS/ISE/sysgen/bin/lin64/xlruntargetfcn.p>xlruntargetfcn at
12
In
/opt/Xilinx/14.6/ISE_DS/ISE/sysgen/bin/lin64/xlGenerateButton.p>xlGenerateButton
at 478
In gen_xps_files at 322
In casper_xps>run_Callback at 155
In casper_xps at 88
In
@(hObject,eventdata)casper_xps('run_Callback',hObject,eventdata,guidata(hObject))
XSG generation complete.
#########################
## Copying base system ##
#########################
Copying base package from:
/home/indrajit/casper/mlib_devel/xps_base/XPS_ROACH_base
########################
## Copying custom IPs ##
########################
##########################
## Creating Simulink IP ##
##########################
##########################
## Creating EDK files ##
##########################
#########################
## Elaborating objects ##
#########################
##############################
## Preparing software files ##
##############################
#########################
## Running EDK backend ##
#########################
Warning: File
'/home/indrajit/ROACH_programs/test2sysgrn/XPS_ROACH_base/implementation/system.bit'
not
found.
> In gen_xps_files at 663
In casper_xps>run_Callback at 155
In casper_xps at 88
In
@(hObject,eventdata)casper_xps('run_Callback',hObject,eventdata,guidata(hObject))
Warning: File
'/home/indrajit/ROACH_programs/test2sysgrn/XPS_ROACH_base/implementation/download.bit'
not
found.
> In gen_xps_files at 664
In casper_xps>run_Callback at 155
In casper_xps at 88
In
@(hObject,eventdata)casper_xps('run_Callback',hObject,eventdata,guidata(hObject))
Xilinx Platform Studio
Xilinx EDK 14.6 Build EDK_P.68d
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
XPS% Loading xmp file system.xmp
INFO:EDK - This project was created with version older than EDK 14.6!!
INFO:EDK - XPS will update the project to EDK 14.6
INFO:EDK - Your current files will be saved with .<old version> extension
Reving up design to EDK 14.6...
WARNING: log file system.log not found
Xilinx EDK 11.1
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.xmp as system_xmp.10
Creating backup of system.mhs as system_mhs.10
sh: dos2unix: command not found
Creating backup of system.mss as system_mss.10
Format revision from 10.1 to 11.1 completed.
Moving all revup related files to 'revup' folder...
Xilinx EDK 11.2
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.xmp as system_xmp.11.1
Creating backup of system.log as system_log.11.1
Creating backup of system.mhs as system_mhs.11.1
Creating backup of system.mss as system_mss.11.1
Format revision from 11.1 to 11.2 completed.
Moving all revup related files to 'revup' folder...
Xilinx EDK 11.3
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.xmp as system_xmp.11.2
Creating backup of system.log as system_log.11.2
Creating backup of system.mhs as system_mhs.11.2
Creating backup of system.mss as system_mss.11.2
Format revision from 11.2 to 11.3 completed.
Moving all revup related files to 'revup' folder...
Xilinx EDK 11.4
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.xmp as system_xmp.11.3
Creating backup of system.log as system_log.11.3
Creating backup of system.mhs as system_mhs.11.3
Creating backup of system.mss as system_mss.11.3
Format revision from 11.3 to 11.4 completed.
Moving all revup related files to 'revup' folder...
Xilinx EDK 11.5
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.xmp as system_xmp.11.4
Creating backup of system.log as system_log.11.4
Creating backup of system.mhs as system_mhs.11.4
Creating backup of system.mss as system_mss.11.4
Format revision from 11.4 to 11.5 completed.
Moving all revup related files to 'revup' folder...
Xilinx EDK 12.0
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.log as system_log.11.5
Format revision from 11.5 to 12.0 completed.
No changes to design files while updating the design from 11.5 to 12.0
Moving all revup related files to 'revup' folder...
Xilinx EDK 12.1
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.log as system_log.12.0
Format revision from 12.0 to 12.1 completed.
No changes to design files while updating the design from 12.0 to 12.1
Moving all revup related files to 'revup' folder...
Xilinx EDK 12.2
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.log as system_log.12.1
Format revision from 12.1 to 12.2 completed.
No changes to design files while updating the design from 12.1 to 12.2
Moving all revup related files to 'revup' folder...
Xilinx EDK 12.3
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.log as system_log.12.2
Format revision from 12.2 to 12.3 completed.
No changes to design files while updating the design from 12.2 to 12.3
Moving all revup related files to 'revup' folder...
Xilinx EDK 12.4
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.log as system_log.12.3
Format revision from 12.3 to 12.4 completed.
No changes to design files while updating the design from 12.3 to 12.4
Moving all revup related files to 'revup' folder...
Xilinx EDK 13.1
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.log as system_log.12.4
Writing system.xmp ...
EDK version 13.1 UPDATE:
Removing Software Project information from system.xmp
Removing XmdStub and BootLoop information from system.xmp
Elf file information is preserved based on InitBram value..
Format revision from 12.4 to 13.1 completed.
Design files have changed while updating the design from 12.4 to 13.1
Creating a back up of 12.4 design files...
Creating backup of system.mhs as system_mhs.12.4
Moving all revup related files to 'revup' folder...
Xilinx EDK 13.2
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.log as system_log.13.1
Format revision from 13.1 to 13.2 completed.
No changes to design files while updating the design from 13.1 to 13.2
Moving all revup related files to 'revup' folder...
Xilinx EDK 13.3
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.log as system_log.13.2
Format revision from 13.2 to 13.3 completed.
No changes to design files while updating the design from 13.2 to 13.3
Moving all revup related files to 'revup' folder...
Xilinx EDK 13.4
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.log as system_log.13.3
Format revision from 13.3 to 13.4 completed.
No changes to design files while updating the design from 13.3 to 13.4
Moving all revup related files to 'revup' folder...
Xilinx EDK 14.1
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.log as system_log.13.4
Format revision from 13.4 to 14.1 completed.
No changes to design files while updating the design from 13.4 to 14.1
Moving all revup related files to 'revup' folder...
Xilinx EDK 14.2
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.log as system_log.14.1
Format revision from 14.1 to 14.2 completed.
No changes to design files while updating the design from 14.1 to 14.2
Moving all revup related files to 'revup' folder...
Xilinx EDK 14.3
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.log as system_log.14.2
Format revision from 14.2 to 14.3 completed.
No changes to design files while updating the design from 14.2 to 14.3
Moving all revup related files to 'revup' folder...
Xilinx EDK 14.4
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.log as system_log.14.3
Format revision from 14.3 to 14.4 completed.
No changes to design files while updating the design from 14.3 to 14.4
Moving all revup related files to 'revup' folder...
Xilinx EDK 14.5
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.log as system_log.14.4
Format revision from 14.4 to 14.5 completed.
No changes to design files while updating the design from 14.4 to 14.5
Moving all revup related files to 'revup' folder...
Xilinx EDK 14.6
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Input File: system.xmp
Creating backup of system.log as system_log.14.5
Format revision from 14.5 to 14.6 completed.
No changes to design files while updating the design from 14.5 to 14.6
Moving all revup related files to 'revup' folder...
Format revision of project to EDK 14.6 completed
Overriding IP level properties ...
Computing clock values...
INFO:EDK - Cannot determine the input clock associated with port :
infrastructure_inst:epb_clk. Clock DRCs will not be performed on this core
and cores connected to it.
INFO:EDK - Cannot determine the input clock associated with port :
infrastructure_inst:epb_clk. Clock DRCs will not be performed on this core
and cores connected to it.
INFO:EDK - Cannot determine the input clock associated with port :
infrastructure_inst:epb_clk. Clock DRCs will not be performed on this core
and cores connected to it.
INFO:EDK - Cannot determine the input clock associated with port :
infrastructure_inst:epb_clk. Clock DRCs will not be performed on this core
and cores connected to it.
INFO:EDK - Cannot determine the input clock associated with port :
infrastructure_inst:epb_clk. Clock DRCs will not be performed on this core
and cores connected to it.
Performing IP level DRCs on properties...
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
Address Map for Processor epb_opb_bridge_inst
(0000000000-0x0000ffff) sys_block_inst opb0
(0x01000000-0x010000ff) test2sysgrn_period opb0
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+++++++++++++++++++++++ WARNING !!! +++++++++++++++++++++++++++++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
WARNING:EDK - Processor epb_opb_bridge_inst has no memory mapped at its reset
vector.
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
INFO:EDK - IPNAME: opb_v20, INSTANCE:opb0 - tool is overriding PARAMETER
C_NUM_MASTERS value to 1 -
/home/indrajit/ROACH_programs/test2sysgrn/XPS_ROACH_base/pcores/opb_v20_v1_10
_c/data/opb_v20_v2_1_0.mpd line 74
INFO:EDK - IPNAME: opb_v20, INSTANCE:opb0 - tool is overriding PARAMETER
C_NUM_SLAVES value to 2 -
/home/indrajit/ROACH_programs/test2sysgrn/XPS_ROACH_base/pcores/opb_v20_v1_10
_c/data/opb_v20_v2_1_0.mpd line 75
Checking platform address map ...
XPS% Evaluating file run_xps.tcl
Xilinx Port::Process Exec Failed:2
ERROR:EDK -
Error while running "gmake -f system.make bits".
Error using gen_xps_files (line 684)
XPS failed.
