Hi Rolando, I'll refer you to Xilinx Sysgen's reference documents. You should be able to get them from their website. They contain all the info you need about those blocks.
The different FFT versions will depend on your board - I'm not familiar with the iBOB, so I'm not sure which FPGA it has on it, but the older FPGAs don't support the newer FFT designs. You can set it up depending on your needs - speed or space. I'd suggest doing a few simulations to get a feel for how the various FFTs work. These don't take too long and will give you a good feel for what's available. Regards, James On Wed, Jan 20, 2016 at 3:40 PM, Rolando Paz <[email protected]> wrote: > Hi > > In the attached picture you can see the fft xilinx blocks I found. > > Which one should I use? > How should I set this block? > > > 2016-01-20 3:06 GMT-06:00 Ryan Monroe <[email protected]>: > >> I don't use the stock CASPER FFTs anymore, but I'm pretty sure that >> there's no way to use them for anything less than {2 complex inputs --OR-- >> 4 real inputs}. If you want less, you can drive an input with a constant >> '0', but resource-wise, they're the same. This is because of algorithmic >> limitations; there is a resource efficiency you gain by doing two complex >> FFTs at once. >> >> This is a time for a streaming Xilinx FFT. >> >> --Ryan >> >> >> On 01/19/2016 09:49 PM, James Smith wrote: >> >> Hi Rolando, >> >> I can't recall that it does, off the top of my head, but the Casper one >> can be set up to use just one input. This is what I've done in the past, I >> think. >> >> Regards, >> James >> >> >> On Wed, Jan 20, 2016 at 7:39 AM, Rolando Paz <[email protected]> wrote: >> >>> Hi James and Andrew >>> >>> Thank for yours advices. >>> >>> I'm trying to recompile the design of Peter McMahon: >>> https://casper.berkeley.edu/wiki/Parspec >>> >>> I'm using these libraries: >>> >>> https://github.com/casper-astro/mlib_devel/tree/mlib_devel-2010-09-20 >>> >>> and I use a virtual machine "windows XP SP3", on ubuntu 14.04LTS, Matlab >>> R2007b, >>> ISE, EDK, SG 10.1, with respective updates, IBOB+QUADC. >>> >>> With this configuration, I can not compile this new design. >>> >>> I'll try with Xilinx FFT... >>> Is there a Xilinx block version for the PFB too? >>> >>> Thank you. >>> >>> >>> >>> 2016-01-19 23:23 GMT-06:00 Andrew Martens < <[email protected]> >>> [email protected]>: >>> >>>> Hi Rolando >>>> >>>> You may want to look at the Xilinx FFT for your use case. The CASPER >>>> FFT is optimised so that minimal resources are used when processing high >>>> bandwidths (either many inputs, or inputs captured at high sample rates). >>>> In this case you may find that the Xilinx FFT actually uses fewer >>>> resources. >>>> >>>> Regards >>>> Andrew >>>> >>>> On Tue, Jan 19, 2016 at 11:11 PM, Rolando Paz <[email protected]> wrote: >>>> >>>>> Hi >>>>> >>>>> Is there any other FFT block that I can use with ADC4x250-8? >>>>> >>>>> https://casper.berkeley.edu/wiki/ADC4x250-8 >>>>> >>>>> I am using the "fft_biplex_real_2x" block, however I need only one >>>>> input of the four that this block has. I placed at zero the others three >>>>> inputs. >>>>> >>>>> I need more FPGA resources from IBOB, and I think using another FFT >>>>> block may be one solution. >>>>> >>>>> Best Regards >>>>> >>>>> RP >>>>> >>>> >>>> >>> >> >> >
