Hi Louise, I have recently done tut1. Once "casper_xps" has been run, you should have the following files generated in your "bit_files" test folder (*.info, *.bit, *.bof, *.gz, and *.fpg). The *.fpg file contains important header information as well as the FPGA progamming file. If you are using casperfpga, which you are, then you will need the *.fpg file. The older version of "mlib_devel" uses the bof file, but at SKA-SA we use the "*.fpg" file with casperfpga. In otherwords, the "fpg" file replaces the "bof" file, in our case. Please rather use the following git repo: " https://github.com/ska-sa/mlib_devel.git" (master branch), as I know this works :).
I am unsure from your email whether the *.fpg file is actually generated or whether you have just not copied it. I will assume it has not been generated as you are using a different repo. Kind Regards, Adam On Tue, May 3, 2016 at 11:51 AM, Louise Forbes <lou...@optinum.co.za> wrote: > Hi all > > > > Newbie here. > > I’m busy working on tut 1 for the ROACH 2 board. I have been able to > connect to the board but when programming it using the command: > > fpga.upload_to_ram_and_program('your_fpgfile.fpg') > > > > I get the following error: > > RuntimeError: 192.168.2.3: no programming informs yet. Odd? > > > > I have made sure that all three files (*.bof, *.bit and *.info) are in the > current working directory. In the tutorial they mention moving the *.fpg > file but then in the example they talk about the *.bof file. > > On successful compilation of your simulink model, a .fpg file will be > created in your_model_name/bit_files/ . Move this to an accessible folder > on the workshop server.S server. > > mv path/to/your/modelfolder/your_model_name/bitfiles/your_boffile.bof > path/to/test/folder > > > > I do not have a *.fpg in the folder mentioned above only a *.bof file. > > Any help would be greatly appreciated. > > > > Thanks > > Regards > > [image: Opti-Num Solutions] > > *Louise Forbes* > > Application Engineer > > *t:* +27 11 325 6238 > > > > *www.optinum.co.za* <http://www.optinum.co.za> > > Seminar <http://www.optinum.co.za/events/SMMBD08?source_id=emailSig> - > System Design: Modelling and Simulation Using MATLAB and Simulink, 17 May > 2016, Johnnesburg > Seminar <http://www.optinum.co.za/events/SMMBD09?source_id=emailSig> - > Hardware-Based Rapid Prototyping using MATLAB and Simulink, 18 May 2016, > Centurion > > [image: http://www.optinum.co.za/_images/LinkedInBug-16px.png] follow us > <http://www.linkedin.com/company/opti-num-solutions> > > > -- Adam Isaacson DBE: FPGA Engineer SKA-SA 3rd Floor The Park Park Road Pinelands 7405 Tel: +27215067300 (W) Fax: +27215067375 (W) Cell: +27825639602