Hi Ho-Cheung, I think in theory simulink does support multiple clock domains (though maybe not truly asynchronous ones?), but I expect in any event it would break the toolflow somewhere if you tried to design such a system only using the simulink designer. This has come up periodically on the maillist, and to my knowledge no-one has followed it through.
The "usual" way to go about what you're describing would be to make a yellow block encapsulating your code, which can instantiate vhdl/verilog of your choice using whatever clock domain(s) you want. If you have data you want to further process in simulink, you can push it through an asynchronous FIFO into the same clock domain as your main simulink design. Unfortunately trying to do this requires getting deep into the guts of the toolflow, which can be a bit of an adventure. If you have code for the system on the second clock domain perhaps someone on the maillist will be able to aid you in packaging it up into the toolflow. Cheers Jack On Thu, 8 Sep 2016 at 14:09 Ho-Cheung Ng <h...@eee.hku.hk> wrote: > Dear All, > > We have a ROACH2-rev2 with an ADC5G Demux1. We are using it to capture > biomedical images with the ADC clock running as the system clock. However > somehow we need another signal from aux_clk input to act as a clock signal > for a small part of the design. Could you let us know how we can do that in > the simulink design flow? > > Thank you very much for your help and answering our question. > > Cheers, > Ho-Cheung NG > > Research Assistant > HKU-CASR, Department of Electrical and Electronic Engineering > The University of Hong Kong > Pokfulam, Hong Kong >
