Hi Jack,

I am using a code similar to the one that you linked in your email.
Although, the code I have does not implement the calibrate_all_delays()
method, I will try using this code.
Yes, I tried to sweep all phases at the same time and also it tried keeping
a, b, c constant and sweeping only d

I am really interested to attend to the training code for harmonizing and
robustifying the adc link discussion. I think I can learn a lot from it!

Thank you,
XB

On Fri, Jul 28, 2017 at 1:49 PM Jack Hickish <jackhick...@gmail.com> wrote:

> Hi Xavier,
>
> At 2.5GHz sampling frequency you might need to calibrate each IO lane
> individually, rather than just sweeping the global clock phase. I don't
> know where you're getting your calibration code from, but if you have a
> calibrate_all_delays method (like at
> https://github.com/jack-h/adc_tests/blob/disentangle/adc5g/src/tools.py)
> you might want to try using that and see if you have any luck.
>
> Cheers
> Jack
>
> PS. I think harmonizing (and robustifying) adc link training code is going
> to be pretty high on the CASPER development priorities, and I'm sure will
> be discussed at the workshop in a couple of weeks.
>
> On Fri, 28 Jul 2017 at 05:06 Xavier Bosch <bruixa.aburrid...@gmail.com>
> wrote:
>
>> Hi Jonathan,
>> Thank you for your response.
>> Unfortunately, I only have one ADC, so I cannot discern between hardware
>> and software error testing each ADC separately.
>> Yes, it is an ROACH2. At the Simulink level, I deleted the ZDOK_1 ADC and
>> I removed some Simulink block that was related to simulation (a block that
>> was reporting data in the workspace) because Matlab was crashing when
>> compiling. These are all the modifications that I did at the CASPER design
>> with respect  the one provided in
>> https://github.com/sma-wideband/adc_tests
>>
>> thank you,
>> XB
>>
>>
>>
>> On Thu, Jul 27, 2017 at 6:02 PM Jonathan Weintroub <
>> jweintr...@cfa.harvard.edu> wrote:
>>
>>> Hi Xavier,
>>>
>>> One obvious question is do you really have just one ADC board?  Or have
>>> you seen the same results on more than one hardware set?
>>>
>>> Also, where you say: "I adapted the CASPER design to match my hardware .
>>> . .” could you give a little more detail on what hardware you are using?
>>> Is this based on a ROACH2?
>>>
>>> Thanks,
>>>
>>> Jonathan
>>>
>>>
>>> On Jul 27, 2017, at 8:02 PM, Xavier Bosch <bruixa.aburrid...@gmail.com>
>>> wrote:
>>>
>>> Hi all,
>>>
>>> I got a ADC 5G V2.0 DMUX1:1 and I decided to evaluate its performance.
>>> As expected the results are poor and its phase needs to be calibrated. I
>>> read the document in here
>>> http://www.worldscientific.com/doi/pdf/10.1142/S2251171714500019  and I
>>> got code from here  https://github.com/sma-wideband/adc_tests I adapted
>>> the CASPER design to match my hardware and I also adapted the calibration
>>> routines.
>>>
>>> The result is always the same: while setting the ADC in test mode,
>>> channels *a, b, c* report 0 glitches while the channel *d* reports
>>> about ~2000 out of the 16384 samples each time. I sweep the phase using
>>> the c*alibrate_mmcm_phase()* function but I never got to reduce the
>>> number of glitches.So the optimal phase does not exist, hence it cannot be
>>> calibrated.
>>>
>>> I am attaching two histograms for ADC_fs=2,5GHz and a signal of input
>>> power fo -10 dBm and 1 MHz and 800 MHz respectively. As you can see,*
>>> a,b,c* channels are withing a reasonable margin while channel *d *gets
>>> out of control.
>>>
>>> Has anyone find a problem like that before? How have you solved? Is
>>> there more available documentation for that part ?
>>>
>>> Thank you,
>>>
>>> XB
>>>
>>>
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>>> <HistogramTest_800MHz_m10dBm_sampling2p5GHz.png>
>>> <HistogramTest_1MHz_m10dBm_sampling2p5GHz.png>
>>>
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