Thanks Aaron,

That seems pretty plausible based on what the downstream logic appears to
be trying to do. Maybe.
If I can verify this, maybe I'll add a docstring...

Cheers
Jack



On Wed, Feb 21, 2018, 9:27 PM Aaron Parsons <[email protected]> wrote:

> My recollection is that Pol1 outputs come for the first N/2 clocks out
> both output ports, even channels on top (in bit reversed order) and odd on
> bottom (also bit reversed order).  Pol2 outputs follow for the next N/2
> clocks, same order.
>
> On Wed, Feb 21, 2018 at 6:04 PM Jack Hickish <[email protected]>
> wrote:
>
>> Howdy,
>>
>> Partly motivated by a search for RAM savings, and partly for fun, I'm
>> looking through the innards of the fft_biplex_real_4x block. Can someone
>> tell me, using short words and/or pictures, what the the relationship
>> between the inputs (pol1, pol2) and the outputs (out1, out2) on the
>> biplex_core block is.
>>
>> I'm in the midst of reverse engineering the block by simulation / staring
>> at the unscrambler / reading about fft biplex implementations, but surely
>> someone must(!) know what this block actually does (or claims to do)?
>>
>> Yours, optimistically,
>>
>> Jack
>>
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> Aaron Parsons
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