# Re: [casper] FFT biplex_core block

```So, I'm sure everyone has been eagerly awaiting the results of
simulations....```
```

For a 16-point biplex_core FFT, with pol1 and pol2 being independent
time-streams, presented in normal time order (i.e., with consecutive time
samples) and output channels defined such that:
chan 0 is DC
chan 7 is the max positive frequency
chan 8 is the negative frequency furthest from DC
chan 15 is the negative frequency closest to DC

The output channel order from the biplex_core is (immediately following the
sync):
out1 = FFT(pol1)[0, 4, 2, 6, 1, 5, 3, 7] followed by FFT(pol2) [0, 4, 2, 6,
1, 5, 3, 7]
out2 = FFT(pol1)[8, 12, 10, 14, 9, 13, 11, 15] followed by FFT(pol2)[8, 12,
10, 14, 9, 13, 11, 15].

These, when bit-reversed, result in:
bit_reverse(out1) = FFT(pol1)[0, 1, 2, 3, 4, 5, 6, 7] followed by FFT(pol2)
[0, 1, 2, 3, 4, 5, 6, 7]
bit_reverse(out2) = FFT(pol1)[8, 9, 10, 11, 12, 13, 14, 15] followed by
FFT(pol2)[8, 9, 10, 11, 12, 13, 14, 15]

How exciting!

Jack

On Wed, 21 Feb 2018 at 22:50 David MacMahon <dav...@berkeley.edu> wrote:

> Hi, Jack,
>
> I haven’t used the biplex_core block in a while, but I believe the inputs,
> pol1 and pol2, are two independent complex input signals. The outputs, out1
> and out2, first output the frequency channels for input pol1, with the low
> half of the band being output in bit reversed order on out1 and the high
> half of the band being output on out2 in bit reversed order. After
> outputting the channels for pol1, out1 and out2 output the channels for
> pol2 in a similar order.
>
> For a 16 channel fft, I think out1 will have channels: pol1[0 4 2 6 1 5 3
> 7] followed by pol2[0 4 2 6 1 5 3 7]. Out2 will have the same output order
> but 8 (ie N/2) channels higher.  I hope that makes sense, but if not I can
> make a better diagram for you tomorrow.
>
> Of course this should be verified with simulation, but I think it’s a good
> starting point. BTW, this assumes the inputs are presented in natural tone
> order at both inputs with the t=0 samples of pol1 and pol2 being presented
> at the respective inputs simultaneously.
>
> Dave
>
> On Feb 21, 2018, at 18:04, Jack Hickish <jackhick...@gmail.com> wrote:
>
> Howdy,
>
> Partly motivated by a search for RAM savings, and partly for fun, I'm
> looking through the innards of the fft_biplex_real_4x block. Can someone
> tell me, using short words and/or pictures, what the the relationship
> between the inputs (pol1, pol2) and the outputs (out1, out2) on the
> biplex_core block is.
>
> I'm in the midst of reverse engineering the block by simulation / staring
> at the unscrambler / reading about fft biplex implementations, but surely
> someone must(!) know what this block actually does (or claims to do)?
>
> Yours, optimistically,
>
> Jack
>
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