Hi Peix Xin, That should work. What mlib_devel are you using? Is your ADC card a demux 1 version?
What ADC yellow block settings? What snap MSSGE block settings (should be clocking from adc0_clk) Are you applying a clock to the ADC card - you can't use the on-board synthesiser with an external ADC. Cheers Jack On Mon, 8 Oct 2018, 6:38 am [email protected], <[email protected]> wrote: > Hi Jack, > > We want use ADC5G card on SNAP board, is there any setting to switch on > ZDOK connector? > The programming is done, however, it returnned 0.0 when we try > fpga.est_brd_clk() > to check the FPGA's clock. > > Best wishes, > Pei Xin > > ------------------------------ > > ========================================== > 裴鑫 (Xin Pei) > 中国科学院新疆天文台 > Xinjiang Astronomical Observatory, CAS > 新疆乌鲁木齐市科学一街150号 > <https://maps.google.com/?q=%E7%A7%91%E5%AD%A6%E4%B8%80%E8%A1%97150%E5%8F%B7&entry=gmail&source=g> > (邮编: 830011) > 150, Science 1-Street > Urumqi, Xinjiang 830011 > China > 电话(Tel): +86-(0)991-3689471 > 传真(Fax): +86-(0)991-3838628 > ========================================== > > -- > You received this message because you are subscribed to the Google Groups " > [email protected]" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to [email protected]. > To post to this group, send email to [email protected]. > -- You received this message because you are subscribed to the Google Groups "[email protected]" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send email to [email protected].
