Hi Nivek, Open the project in Vivado, then on the left under Implementation, click “Open Implemented Design”. Above the image of the device utilization, click the “Project Summary” tab. Scroll down to see the box that says Utilization, and then click “Table”.
I hope this helps! I can send more detail or screenshots if that would help. Cheers, Kathryn ________________________________ From: Nivek Ghazi <[email protected]> Sent: Friday, June 21, 2019 4:29 AM To: [email protected] Subject: [casper] FPGA resource usage Hey guys, I have a quick question, how do you check amount of resources (bram, dsp slices, etc) your design is using? I'm using Vivado 2016.4 and the design is for a SNAP board. cheers, Nivek -- You received this message because you are subscribed to the Google Groups "[email protected]" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]<mailto:[email protected]>. To view this discussion on the web visit https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CAG8hsvkqnu9rSJk01xMqRDLd-OcENo4UiA6BsdVJfARc9fN6qQ%40mail.gmail.com<https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CAG8hsvkqnu9rSJk01xMqRDLd-OcENo4UiA6BsdVJfARc9fN6qQ%40mail.gmail.com?utm_medium=email&utm_source=footer>. -- You received this message because you are subscribed to the Google Groups "[email protected]" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/BYAPR03MB4677C9F20631204E544E8F68D8E70%40BYAPR03MB4677.namprd03.prod.outlook.com.
