Awesome, thanks.
Nivek
On 2019/06/24 10:57, Adam Isaacson wrote:
Hi Nivek,
For more detailed resource utilisation stats then open vivado. Click
on "open implemented design" and then click on "Report Utilization".
This will generate a very detailed resource utilisation down to any
firmware level.
Kind regards,
Adam Isaacson
South African Radio Astronomy Observatory (SARAO)
Hardware Manager
Cell: (+27) 825639602
Tel: (+27) 215067300
email: [email protected] <mailto:[email protected]>
On Mon, Jun 24, 2019 at 9:27 AM Jason Manley <[email protected]
<mailto:[email protected]>> wrote:
If you're too impatient to open the design in Vivado, the text
reports are still generated during compile:
<myslxfolder>/myproj/myproj.runs/impl_1/top_utilization_placed.rpt
In that same folder, you'll also find the timing report,
top_timing_summary_routed.rpt, which is also useful.
Jason
> On 21 Jun 2019, at 23:44, Nivek Ghazi <[email protected]
<mailto:[email protected]>> wrote:
>
> Hey Kathryn,
>
> Worked perfectly, thanks.
>
> Nivek
>
> On Fri, Jun 21, 2019 at 6:31 PM Plant, Kathryn A.
<[email protected] <mailto:[email protected]>> wrote:
> Hi Nivek,
> Open the project in Vivado, then on the left under
Implementation, click “Open Implemented Design”. Above the image
of the device utilization, click the “Project Summary” tab. Scroll
down to see the box that says Utilization, and then click “Table”.
>
> I hope this helps! I can send more detail or screenshots if that
would help.
>
> Cheers,
> Kathryn
> From: Nivek Ghazi <[email protected]
<mailto:[email protected]>>
> Sent: Friday, June 21, 2019 4:29 AM
> To: [email protected] <mailto:[email protected]>
> Subject: [casper] FPGA resource usage
>
> Hey guys,
>
> I have a quick question, how do you check amount of resources
(bram, dsp slices, etc) your design is using? I'm using Vivado
2016.4 and the design is for a SNAP board.
>
> cheers,
> Nivek
>
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