If you are using Vivado beyond 2016.4 I don’t think they have removed that feature from the FIR IP. Now if the ability is there in Simulink is a different question. I have attached a screenshot show how to configure the sampling for the FIR to take in 4 samples per clock. I hope this helps,
John Gard NIST From: Dan Werthimer <[email protected]> Sent: Thursday, June 27, 2019 9:14 AM To: CASPER Mailing List <[email protected]> Subject: Re: [casper] FIR and decimating CIC filter jason, some info on SSR on pages 114-117 of: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug897-vivado-sysgen-user.pdf<https://gcc01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.xilinx.com%2Fsupport%2Fdocumentation%2Fsw_manuals%2Fxilinx2018_3%2Fug897-vivado-sysgen-user.pdf&data=02%7C01%7Cjohnathon.gard%40nist.gov%7C1da730d5a74f469239e608d6fb1225e7%7C2ab5d82fd8fa4797a93e054655c61dec%7C1%7C1%7C636972452699566950&sdata=dlKVG%2FNt66rv6FlsPI8EDefFZO0xYOigbZ4Lo7dkOdk%3D&reserved=0> dan Dan Werthimer Marilyn and Watson Alberts Chair Astronomy Dept and Space Sciences Lab University of California, Berkeley On Thu, Jun 27, 2019 at 8:07 AM Jason Manley <[email protected]<mailto:[email protected]>> wrote: That's an interesting development that I wasn't aware of! As it turns out, we're using Vivado 2018.2, but this might be a strong motivator to switch to the newer tools. Thanks for the heads-up. I'll definitely look into it. Jason > On 27 Jun 2019, at 17:05, Forbes, David C - (dforbes) > <[email protected]<mailto:[email protected]>> wrote: > > Jason, > > Xilinx has started to offer an SSR (Super Sample Rate) DSP library with > Vivado 2018.3, which CASPER would do well to migrate towards. But if you're > stuck in the old toolchain, then I can't help you. > > > David Forbes > Arizona Radio Observatory > Tucson, AZ > W: 520-626-1361 C: 520-989-1491 > > -----Original Message----- > From: Jason Manley <[email protected]<mailto:[email protected]>> > Sent: Thursday, June 27, 2019 7:51 AM > To: Casper Lists <[email protected]<mailto:[email protected]>> > Subject: [casper] FIR and decimating CIC filter > > Hi CASPERites > > Has anyone implemented a decimating CIC filter on a CASPER platform? How > 'bout a conventional IIR or FIR filter? We're after ones that accept parallel > input samples; the Xilinx one doesn't seem to do wideband signals. > > We're looking at options for a new digital downconverter. Please let me know > if you've got something you could share with us to use. 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