Hi

I implemented a similar library of vector processing primitives (the Bus
subsection in the library) a few years ago when we upgraded the PFB.
Unfortunately, Simulink has upper limits on the width of buses, and drawing
area. We have not been able to implement large-number-of-tap pfb_firs
because of the bus restriction (if I recall correctly, the limit is 4096
bits). As we move to higher bandwidths we will have to hack around this
restriction more unless Mathworks changes things. I would guess using the
Xilinx primitives will give the same issues.

Regards
Andrew

On Thu, Jun 27, 2019 at 5:22 PM Forbes, David C - (dforbes) <
[email protected]> wrote:

> Jason,
>
> Yes, it's quite a big thing, and it's not publicized at all. I had to dig
> through the DSP user guides to find it.
>
> They have parallel FIR filters and parallel FFTs and all the good things
> that people used to have to write from scratch.
>
> I'd like to see CASPER adopt the new Xilinx tools as a way to build DSP
> gateware in the future, as the cellphone base station providers have
> finally caught up to radio astronomy in bandwidth. Having the telecom
> industry pushing the tools forward will get a lot accomplished, with much
> less effort expended by our gang.
>
>
> David Forbes
> Arizona Radio Observatory
> Tucson, AZ
> W: 520-626-1361  C: 520-989-1491
>
> -----Original Message-----
> From: Jason Manley <[email protected]>
> Sent: Thursday, June 27, 2019 8:08 AM
> To: Casper Lists <[email protected]>
> Subject: Re: [casper] FIR and decimating CIC filter
>
> That's an interesting development that I wasn't aware of! As it turns out,
> we're using Vivado 2018.2, but this might be a strong motivator to switch
> to the newer tools.
>
> Thanks for the heads-up. I'll definitely look into it.
>
> Jason
>
>
> > On 27 Jun 2019, at 17:05, Forbes, David C - (dforbes) <
> [email protected]> wrote:
> >
> > Jason,
> >
> > Xilinx has started to offer an SSR (Super Sample Rate) DSP library with
> Vivado 2018.3, which CASPER would do well to migrate towards. But if you're
> stuck in the old toolchain, then I can't help you.
> >
> >
> > David Forbes
> > Arizona Radio Observatory
> > Tucson, AZ
> > W: 520-626-1361  C: 520-989-1491
> >
> > -----Original Message-----
> > From: Jason Manley <[email protected]>
> > Sent: Thursday, June 27, 2019 7:51 AM
> > To: Casper Lists <[email protected]>
> > Subject: [casper] FIR and decimating CIC filter
> >
> > Hi CASPERites
> >
> > Has anyone implemented a decimating CIC filter on a CASPER platform? How
> 'bout a conventional IIR or FIR filter? We're after ones that accept
> parallel input samples; the Xilinx one doesn't seem to do wideband signals.
> >
> > We're looking at options for a new digital downconverter. Please let me
> know if you've got something you could share with us to use. If not, we'll
> have to start modding the PFB_FIR and existing DDC library blocks for our
> needs.
> >
> > Jason Manley
> > DSP Manager
> > SKA-SA
> >
> > Cell: +27 82 662 7726
> > Work: +27 21 506 7300
> >
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