Hi Everyone, I have encountered a weird issue with my red pitaya.
I tried uploading tut_intro. If we assign 1 to counter_ctrl, the lower slice, which should be the LSB, gives 0. If we assign 2^24 to counter_ctrl, the lower slice gives 1 implying there is an offset of 24 bits. We also noticed that boolean signals come through casperfpga as 2^24 when they are true. I haven't modified the tut_intro fpg or slx file in any way. I am using Vivado 2019a and Matlab 2018a. 10 and 14 bits red pitayas appear to have similar behavior. Is this a problem with our red pitaya firmware, casperfpga or our local toolflow? Thank you for your help in advanced. Sincerely, Will -- You received this message because you are subscribed to the Google Groups "[email protected]" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/e8d4c1d6-7665-467b-aecc-09d24d83846d%40lists.berkeley.edu.
