Hi Will,

This sounds like the endianess issue we encountered. The latest version of
casperfpga in casper-astro should have this proper fix. What git hash
version of casperfpga are you using?

One way to check is to go to casper-astro/tutorials_devel (workshop2019)
branch and use the casperfpga git hash it references or just use the
tutorials_devel git repo. It has everything you need just to do a sanity
check.

My feeling is that we did fix this.

HTH,

Adam


On Tue, 27 Aug 2019, 10:20 PM William Emery, <[email protected]>
wrote:

> Hi Everyone,
>
> I have encountered a weird issue with my red pitaya.
>
> I tried uploading tut_intro.  If we assign 1 to counter_ctrl, the lower
> slice, which should be the LSB, gives 0.  If we assign 2^24 to
> counter_ctrl, the lower slice gives 1 implying there is an offset of 24
> bits.  We also noticed that boolean signals come through casperfpga as 2^24
> when they are true.
>
> I haven't modified the tut_intro fpg or slx file in any way.  I am using
> Vivado 2019a and Matlab 2018a.  10 and 14 bits red pitayas appear to have
> similar behavior.
>
> Is this a problem with our red pitaya firmware, casperfpga or our local
> toolflow?
>
> Thank you for your help in advanced.
>
> Sincerely,
> Will
>
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