Hi everyone, Short update: Problem is solved and the design is working as expected.
I was using the ska-sa/casperfpga <https://github.com/ska-sa/casperfpga> repository, when I installed the casper-astro/casperfpga <https://github.com/casper-astro/casperfpga> everything start working as expected. Thanks to Amish Patel for pointing out what casperfpga version I should use! Thank you for your time XB On Tue, Sep 10, 2019 at 4:35 PM Xavier Bosch <[email protected]> wrote: > Hi everyone, > > I been extensively testing the adc_snap problem and I have not been able > to figure it out. > I am using a Rpi and adc0_clk (fclk=10 MHz, I was previously using 50 MHz) > and simplified to the minimum expression the diagram: ADC+ snap-block > > - Results from testing the option of using 12 ADC with the > configuration [1,2,3,4], I get the pattern 1,1, 2,2, | 3,3, 4,4 when it > should be 1,2,3,4, | 1,2,3,4 . Being {adc1, adc2, adc3, adc4}@t=0| > {adc1, adc2, adc3, adc4}@t=1 > - Results from testing the option of using 6 ADC with the > configuration [1,1,3,3], I get the pattern 1,1,1,1 | 3, 3, 3, 3 when it > should be 1,1,3,3| 1,1,3,3. Being {adc1, adc2, adc3, adc4}@t=0| > {adc1, adc2, adc3, adc4}@t=1 > - Results from testing the option of using 3 ADC with the > configuration [1,1,1,1] it works fine. > > > I tested all the ADC configuration possibilities, the ones that make sense > and even what does not make sens. I am very much convinced that this is not > an ADC miss-config. > > QUESTIONS > > - Any other idea/test that I could run to see what is the source of > such behavior? > - Anyone is using the SNAP in a 12 ADC or 6 ADC configuration? I am > guessing that a lot of people, but just to confirm it. > - Could you tell me what version of mlib_devel library are you using? > - What casperfpga library are you using ? (I updated the last > casperfpga library version with identical results) > > Thank you, > > XB > > > > > On Mon, Sep 9, 2019 at 1:35 PM Xavier Bosch <[email protected]> > wrote: > >> Hi Jack >> >> I did multiple extra test, all of them with the same result: outputs are >> multiplexed in time. >> I am using casperfpga 284a4ba from >> https://github.com/ska-sa/casperfpga.git >> >> Thanks, >> XB >> >> >> On Fri, Sep 6, 2019 at 11:52 AM Jack Hickish <[email protected]> >> wrote: >> >>> Hi Xavier, >>> >>> The only yellow block info you'll find is by looking at the code. When >>> configured properly for a given mode, the block doesn't time multiplex >>> multiple ADC channels, it does what you expected it to do. I just >>> checked the init code we use for HERA, and it's pretty much the same >>> as you, though we use inputs 1 and 3 (adc.selectInput([1,1,3,3]). I'm >>> not sure if this is significant (I don't think it should be). >>> What version of casperfpga are you using? >>> Cheers >>> Jack >>> >>> On Wed, 4 Sep 2019 at 09:18, Xavier Bosch <[email protected]> >>> wrote: >>> > >>> > Hi all, >>> > >>> > I been using SNAP board (a regular-standard board) for a while now in >>> a 3-ADC @ 800 MHz configuration mode. I would like to use it in a 6-ADC @ >>> 500 MHz configuration mode and I am having some trouble understanding what >>> is going on. I read the HMCAD1511 datasheet. >>> > >>> > ADC configuration with [1,1,2,2] (see the whole ADC calibration >>> function at the end of this email) >>> > >>> > I connected a snap block (dataloggers) to the yellow-block >>> (snap_adc) to record time series of the collected data. What I see is that >>> ADC0 and ADC1 outputs are not spitted between a0 and a1 (yellow block) and >>> a2 and a2, respectively. >>> > Instead, what I find is that they are time multiplexed, ie. at t0 I >>> have that ADC0 is at a0, a1, a2 and a4, and at t1 I have ADC1 at a0, a1, >>> a2 and a4 >>> > >>> > See attached picture of 8 consecutive samples of a0, a1, a2 and a3 >>> with only ADC0 connected (figure ADC0_ch0) and then ADC0 and ADC1 >>> connected (Figure_ch0_ch1), ie. First row is t0, second row is t1) >>> > >>> > The HMCAD1511 datasheet does not show a time multiplexed output but a >>> parallel output. I do not know how the yellow block is implemented. Where I >>> could find more information about the yellow block implementation? >>> > Is that the expected yellow block output? If the yellow block time >>> multiplexes the ADC0 and ADC1 then how do you synchronize the channels with >>> the rest of the design? >>> > >>> > >>> > code that I use to configure/calibrate the ADCs >>> > >>> > def init_adc(self): >>> > >>> > self.sample_rate=500 >>> > >>> > adc = casperfpga.snapadc.SNAPADC(self.fpga,ref=50) >>> > >>> > if adc.init(self.sample_rate, numChannel=2,resolution=8) == 0: >>> > >>> > print "ADC calibrated! " >>> > >>> > else: >>> > >>> > print "ERROR ->>> ADC NOT calibrated! " >>> > sys.exit(0) >>> > >>> > #adc.selectADC(0) >>> > >>> > adc.adc.selectInput([1,1,2,2]) >>> > >>> > >>> > >>> > Best, >>> > >>> > XB >>> > >>> > >>> > >>> > >>> > >>> > -- >>> > You received this message because you are subscribed to the Google >>> Groups "[email protected]" group. >>> > To unsubscribe from this group and stop receiving emails from it, send >>> an email to [email protected]. >>> > To view this discussion on the web visit >>> https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CAMehrA33bgtX2u_tAA0fQLsh7FbmeAMx1y%3DRDQ%2BmB79fTKFOJw%40mail.gmail.com >>> . >>> >>> -- >>> You received this message because you are subscribed to the Google >>> Groups "[email protected]" group. >>> To unsubscribe from this group and stop receiving emails from it, send >>> an email to [email protected]. >>> To view this discussion on the web visit >>> https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CAG1GKSmiv_Ci%3DU88PoECMM8b_AcWWCvmCqSggyQB5RXJV9twQw%40mail.gmail.com >>> . >>> >> -- You received this message because you are subscribed to the Google Groups "[email protected]" group. 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