On Friday, February 14, 2020 at 12:45:21 AM UTC-7, henno wrote: > > Hi John, > > I have a few questions / remarks / suggestions: > > Do you observer CRC errors in both directions or is it only from FPGA to > PC? >
I think it is in both directions, but I haven't exhaustively tested the PC to FPGA path. > > In RGMII, the TX and RX clocks are not synced, but in loopback mode it is, > which might point to a metastability issue when you connect to the PC. > > Thanks. This is a good clue and one which I had not thought of. I will explore this avenue. I had thought that since my loopback showed good results then that part was OK. > Is the PCB a custom board or a DEV-KIT? The length matching of the traces > is important, but the TX clock skew to the PHY is also important, since DDR > is used. > It's a custom PCB. We matched the traces to about 10 ps of delay. The tx clock is set to a 2 ns offset in the Xilinx core using a 90 degree phase shift on the 125 MHz clock. I haven't experimented with changing the phase, or of the delay on the rx clock to rx data. The PHY has an adjustment for these, but it's quantized in 0.5 ns, and that might not be fine enough. Thanks for the ideas. Looks like a fun weekend in store for me. :) John > > Best, > HK > > On Thu, Feb 13, 2020 at 11:50 PM John Ford <[email protected] > <javascript:>> wrote: > >> Hi all. >> >> I'm designing an FPGA based instrument control system with a gigabit >> Ethernet port. It should be easy to make this work, but alas, it's giving >> me fits. >> >> I have a Xilinx Artix-7 FPGA on the board, driving a TI PHY using the >> RGMII interface from the Xilinx tri-mode Ethernet MAC core. It mostly >> works, but not completely reliably. >> >> If I setup the PHY in analog loopback mode, which loops the packets back >> to the FPGA, I can run packets at full line rate all day with no errors. >> So I'm somewhat convinced that the RGMII link is good between the FPGA and >> the PHY. >> >> If I link the board up to a computer (I've tried a couple different >> ones,) I get ~5 to 10% of the packets being received with CRC errors. >> >> Is there anyone on the list that's designed Gigabit Ethernet hardware >> that could give me a hand with this? Any ideas that jump out? I've run >> our of ideas. >> >> Thanks for any advice. If you are or know a good Gigabit Ethernet guru >> for hire, let me know! >> >> John >> >> -- >> You received this message because you are subscribed to the Google Groups >> "[email protected] <javascript:>" group. >> To unsubscribe from this group and stop receiving emails from it, send an >> email to [email protected] <javascript:>. >> To view this discussion on the web visit >> https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CABmH8B-suUrcdbRYvUpCqF5NuqSE8mboYxFcGj0Mv%3DGMjDoVcQ%40mail.gmail.com >> >> <https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CABmH8B-suUrcdbRYvUpCqF5NuqSE8mboYxFcGj0Mv%3DGMjDoVcQ%40mail.gmail.com?utm_medium=email&utm_source=footer> >> . >> > -- You received this message because you are subscribed to the Google Groups "[email protected]" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/32852c07-85b6-4c0f-b1dc-85e4574d2dc5%40lists.berkeley.edu.
