Hi John,

Another thing to check for is a missing or incorrect timing constraint -
Vivado constraints wizard may pick up something (tsu, th, tco).

Best
HK

On Wed, Feb 19, 2020 at 12:09 PM Borsenberger Jean <
jean.borsenber...@obspm.fr> wrote:

>     Hello
>
> Incorrect cabling would lead to force to dowgrade giga to fast, or no
> connection at all.
> With that hi level of CRC, I would first address a connector weakness
> (contact not complete), or a lack of shielding in a perturbated area, and
> most unlikely false pairing inside the cable ( all pairs are individualy
> twisted, an if you mix two pairs...)
> Try a cat 7 cable ( thick shielding of each pair, thick shielding of the
> whole), and see what happens.
> Regards
> Jean
> Le Mercredi, Février 19, 2020 03:33 CET, Ross Martin <ross.mar...@ieee.org>
> a écrit:
>
>
> Hi John,
>
> I'll throw out a possibility.  Perhaps the cabling isn't correct and
> you're only getting connectivity on one of the two wires in the
> differential pair.  This would work *sometimes*, which is about what you're
> seeing.
>
> This might happen if you wired your own cables or connectors and laid them
> out logically.  Cat5 connectors have an unusual pinout that's not exactly
> logical. (At least not logical to me.)
>
> Regards,
>
> Ross
>
> On Tue, Feb 18, 2020, 5:47 PM John Ford <jmfor...@gmail.com> wrote:
>
>>
>>
>> I did some more testing, and I wanted to share the results.  I have done
>> reverse loopback testing, sending the packets from the host to the PHY,
>> where it loops back inside the PHY, and is returned to the host.  This
>> shows packet loss on the order of the total packets being lost.  So this
>> bit of information leads me back to the analog side of things.  Power
>> supply?  oscillator?  PCB layout?  Our board house did 100 ohm
>> differential, and tested it, and it is better than 10%.  The traces in the
>> pairs are matched to a couple of mils.  Here's a drawing of the testing
>> that's been done first the digital and analog forwarded loopback, then the
>> reverse loopback.
>>
>>
>>
>> On Fri, Feb 14, 2020 at 12:52 AM Henno Kriel <he...@ska.ac.za> wrote:
>>
>>> Hi John,
>>>
>>> I have a few questions / remarks / suggestions:
>>>
>>> Do you observer CRC errors in both directions or is it only from FPGA to
>>> PC?
>>>
>>> In RGMII, the TX and RX clocks are not synced, but in loopback mode it
>>> is, which might point to a metastability issue when you connect to the PC.
>>>
>>> Is the PCB a custom board or a DEV-KIT? The length matching of the
>>> traces is important, but the TX clock skew to the PHY is also important,
>>> since DDR is used.
>>>
>>> Best,
>>> HK
>>>
>>> On Thu, Feb 13, 2020 at 11:50 PM John Ford <jmfor...@gmail.com> wrote:
>>>
>>>> Hi all.
>>>>
>>>> I'm designing an FPGA based instrument control system with a gigabit
>>>> Ethernet port.  It should be easy to make this work, but alas, it's giving
>>>> me fits.
>>>>
>>>> I have a Xilinx Artix-7 FPGA on the board, driving a TI PHY using the
>>>> RGMII interface from the Xilinx tri-mode Ethernet MAC core.  It mostly
>>>> works, but not completely reliably.
>>>>
>>>> If I setup the PHY in analog loopback mode, which loops the packets
>>>> back to the FPGA, I can run packets at full line rate all day with no
>>>> errors.  So I'm somewhat convinced that the RGMII link is good between the
>>>> FPGA and the PHY.
>>>>
>>>> If I link the board up to a computer (I've tried a couple different
>>>> ones,) I get ~5 to 10% of the packets being received with CRC errors.
>>>>
>>>> Is there anyone on the list that's designed Gigabit Ethernet hardware
>>>> that could give me a hand with this?  Any ideas that jump out?  I've run
>>>> our of ideas.
>>>>
>>>> Thanks for any advice.  If you are or know a good Gigabit Ethernet guru
>>>> for hire, let me know!
>>>>
>>>> John
>>>>
>>>>
>>>>
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