Dear Aravind,

Did you know there is an existing, working and completed slx file
(tut_adc_dac.slx) for this tutorial in:

https://github.com/casper-astro/tutorials_devel/tree/master/red_pitaya/tut_adc_dac

I would compare that file with your file attached and look for any
differences. I am also going to look at your file and see if I can spot
anything. Stay tuned.

Kind regards,

Adam Isaacson
South African Radio Astronomy Observatory (SARAO)
Hardware Manager
Cell: (+27) 825639602
Tel:  (+27) 215067300
email: [email protected]



On Tue, Apr 7, 2020 at 1:53 AM Aravind Venkitasubramony <
[email protected]> wrote:

> Hi
>
> I followed the tutorial and created the .slx file. While compiling I got
> these errors from simulink.
>
>
> Matching "From" for "Goto" 'rp_tut2/adc_in_snap/ss/goto_ss_we1' not found
> [4 similar]
> Component:Simulink | Category:Block warning
> Output port 1 of 'rp_tut2/dac/rp_tut2_dac_dac0_data_i_in' is not
> connected. [8 similar]
> Component:Simulink | Category:Block warning
> The input type propagated to this block did not match the specified type.
>   Expected Type: Bool
>   Actual Type: Fix_10_0
>
> Error occurred during "Rate and Type Error Checking".
>
>
> Reported by:
>   'rp_tut2/adc_in_snap/assert_b'
> A summary of Sysgen errors has been written to
> '/home/cet/RP_work/models/rp_tut2/rp_tut2_sysgen_error.log'
>
> Reported by:
>   'rp_tut2/adc_in_snap/assert_b'
>
> I also notice that I do not get the "in_adc_data_valid" port shown in the
> in the bit field snap block on the tutorial page. Other than that, I
> recreated everything as mentioned in the tutorial page. I have attached the
> .slx  and the sysgen error log files also alongwith
>
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