Hello casperites, nice to see the list is still active! Wanted to ask around for info here on SPEAD.
Would be happy for any helpful pointers towards public reusable SPEAD 64_40 Verilog/VHDL implementations, or even just verification benches, to ease devel and validation of a hardware receiver implementation. If someone has experience from writing a (non/)public implementation, an estimate of hours or FTEs would be very helpful too! I dug through the CASPER and SKA repositories so far. There are mentions of SPEAD in for example the Simulink models. No actual low-level nor high-level implementations though. Have checked OpenCores as well. There is an SKA memo [1] that does mention implementations, but these refer to Python/C++. Looking at the C++ code, it does not look fit for using in HLS really... Wondering - are there public SPEAD implementations for FPGA available somewhere? Our interest in SPEAD is due to the Effelsberg telescope, and certain hardware and new cm-wave receivers there. Those receivers have integrated direct RF sampling and they transmit SPEAD over 40G/100G & UDP. To permit VLBI compatible observations with those new cm-wave receivers too, without dropping back into an analog IF, the initial plan was to have a software extension in the GPU cluster to convert the full radio bandwidth into VLBI-standard data. That plan got revised, however, and now an existing FPGA-based VLBI backend should be extended instead by the backend firmware engineers, so that it can accept SPEAD-delivered raw sample data over parallel 10G links. Looking at the SPEAD rev 0 document, a transmitter would appear lightweight to implement and seems quite FPGA-suited. A receiver looks somewhat more challenging on FPGA, easy in C++/Python though. The complex bits if I see correctly would be large buffering for Heap reconstruction, and an interpreter engine to cope with the varying order and length of the 'ItemDescriptors' to be generic enough and avoid code maintenance if anything on the other side ie transmitter side is upgraded/altered. Could also be I'm mistaken, and a receiver is easy on FPGA? Would appreciate your input and experiences on this matter! :-) many thanks in advance, regards, Jan [1] http://ska-sdp.org/sites/default/files/attachments/sdp_memo_046_experiences_with_the_spead_protocol.pdf -- You received this message because you are subscribed to the Google Groups "[email protected]" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/3048e212-c535-48a3-8800-9a1a3f7c1368%40lists.berkeley.edu.
