Hello Heystek,

You will have to go through the timing reports and see which signal path is
failing timing, and by how much.

Once you have an idea, you will need to sprinkle delay blocks and / or
adjust latencies in your logic to get to a point where the place-and-route
can find a layout that satisfies timing requirements.

It's a bit of a black art, always hit and miss for me.

Regards,
James




On Wed, Aug 26, 2020 at 8:00 AM Heystek Grobler <[email protected]>
wrote:

> Good day everyone
>
> I am running a design but ran into this problem:
>
> xflow done!
> touch __xps/system_routed
> xilperl /opt/Xilinx_ISE/14.7/ISE_DS/EDK/data/fpga_impl/observe_par.pl
> -error yes implementation/system.par
> Analyzing implementation/system.par
>
> ********************************************************************************
> ERROR: 1 constraint not met.
>
> PAR could not meet all timing constraints. A bitstream will not be
> generated.
>
> To disable the PAR timing check:
>
> 1> Disable the "Treat timing closure failure as error" option from the
> Project Options dialog in XPS.
>
> OR
>
> 2> Type following at the XPS prompt:
> XPS% xset enable_par_timing_error 0
>
> ********************************************************************************
> system.make:140: recipe for target 'implementation/system.bit' failed
> gmake: *** [implementation/system.bit] Error 1
> ERROR:EDK -
>    Error while running "gmake -f system.make bits".
>
> It seems to be a timing constraint.
>
> How do I deal with this?
>
> Thanks for the help!
>
> Heystek
>
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