Hi Heystek, One other question: How fast is the clock rate you are trying to compile? For ROACH2, if you're above a 200MHz clock (and definitely if you're above 250MHz), or if you have a very full design, I've often found that you need to use PlanAhead to make the design meet timing.
A (very outdated) set of instructions on how to run planAhead is here: https://casper.ssl.berkeley.edu/wiki/Tutorial_PlanAhead Opening up the design in PlanAhead should give you the option to interact with the failing timing paths manually. If you just wanted to browse the timing report, it should be under: <model_name>/XPS_ROACH2_BASE/implementation/system_map.twr Cheers, Jonathon On Thu, 27 Aug 2020 at 15:24, David MacMahon <[email protected]> wrote: > Hi, Heystek, > > I think the build will generate a timing report in a file that ends with > ".twr". If it's not, you can generate one using the "trce" utility (part > of ISE). This will tell you how many nets failed timing and show details > of the N worst offenders (I think N defaults to 3 or maybe 10?). If you > have a large number of nets failing timing it's likely more difficult to > rectify, but if there's only a few it's usually not too hard to resolve. > > Happy hunting, > Dave > > On Aug 27, 2020, at 04:46, Heystek Grobler <[email protected]> > wrote: > > Hey Andrew and James and everyone. > > After probed around and the following timing constraint is not met: > > TS_sys_clk_n > > I assume that my system clock is not running at an appropriate frequency? > > Thanks for the help! > > Heystek > > > > On Wed, Aug 26, 2020 at 10:59 AM Andrew Martens <[email protected]> wrote: > >> Hi Heystek >> >> Output reports and their location change over versions, between ISE and >> Vivado etc. I think the output reports for ISE are located in the >> 'implementation' folder. I think the timing related ones have 'timing' in >> the name... A quick Google search of the error will help. >> >> Note that there are archives of the mailing list available at >> https://www.mail-archive.com/[email protected]/ - your problem >> has probably been answered already previously. >> >> Regards >> Andrew >> >> On Wed, Aug 26, 2020 at 10:49 AM Andrew van der Byl <[email protected]> >> wrote: >> >>> Hi Heystek, >>> >>> It's possible that you then have another issue that causes the build >>> process to exit prior to generating that file. You'll need to debug that >>> first. >>> >>> Regards, >>> Andrew >>> >>> On Wed, Aug 26, 2020 at 10:40 AM Heystek Grobler < >>> [email protected]> wrote: >>> >>>> Hey Andrew >>>> >>>> It is strange, I cant seem to locate top_timing_summary_routed.rpt >>>> >>>> I am running Matlab 2012B with ISE 14.7 >>>> >>>> >>>> >>>> On 26 Aug 2020, at 10:27, Andrew van der Byl <[email protected]> wrote: >>>> >>>> Hi Heystek, >>>> >>>> 1) Navigate to your project folder >>>> 2) Then go to and open: <project_folder>/myproj/myproj.runs/impl_1/ >>>> top_timing_summary_routed.rpt >>>> >>>> Just a note - this file is usually fairly large as text files go ~20MB. >>>> >>>> Regards, >>>> Andrew >>>> >>>> On Wed, Aug 26, 2020 at 10:22 AM Heystek Grobler < >>>> [email protected]> wrote: >>>> >>>>> Hey James and Andrew >>>>> >>>>> Thank you so much for the advice! >>>>> >>>>> @Andrew, this might be a stupid question, but where do I locate the >>>>> top_timing_summary_routed.rpt >>>>> file? >>>>> >>>>> Heystek >>>>> >>>>> >>>>> On 26 Aug 2020, at 10:17, Andrew van der Byl <[email protected]> wrote: >>>>> >>>>> Hi Heystek, >>>>> >>>>> Have a look in top_timing_summary_routed.rpt and search for 'VIOLATED' >>>>> - this usually shows up which paths are hurting your design. Then, as >>>>> James >>>>> said, start pipeling your design. >>>>> >>>>> Hope this helps. >>>>> >>>>> Regards, >>>>> Andrew >>>>> >>>>> On Wed, Aug 26, 2020 at 10:13 AM James Smith <[email protected]> wrote: >>>>> >>>>>> Hello Heystek, >>>>>> >>>>>> You will have to go through the timing reports and see which signal >>>>>> path is failing timing, and by how much. >>>>>> >>>>>> Once you have an idea, you will need to sprinkle delay blocks and / >>>>>> or adjust latencies in your logic to get to a point where the >>>>>> place-and-route can find a layout that satisfies timing requirements. >>>>>> >>>>>> It's a bit of a black art, always hit and miss for me. >>>>>> >>>>>> Regards, >>>>>> James >>>>>> >>>>>> >>>>>> >>>>>> >>>>>> On Wed, Aug 26, 2020 at 8:00 AM Heystek Grobler < >>>>>> [email protected]> wrote: >>>>>> >>>>>>> Good day everyone >>>>>>> >>>>>>> I am running a design but ran into this problem: >>>>>>> >>>>>>> xflow done! >>>>>>> touch __xps/system_routed >>>>>>> xilperl /opt/Xilinx_ISE/14.7/ISE_DS/EDK/data/fpga_impl/ >>>>>>> observe_par.pl -error yes implementation/system.par >>>>>>> Analyzing implementation/system.par >>>>>>> >>>>>>> ******************************************************************************** >>>>>>> ERROR: 1 constraint not met. >>>>>>> >>>>>>> PAR could not meet all timing constraints. A bitstream will not be >>>>>>> generated. >>>>>>> >>>>>>> To disable the PAR timing check: >>>>>>> >>>>>>> 1> Disable the "Treat timing closure failure as error" option from >>>>>>> the Project Options dialog in XPS. >>>>>>> >>>>>>> OR >>>>>>> >>>>>>> 2> Type following at the XPS prompt: >>>>>>> XPS% xset enable_par_timing_error 0 >>>>>>> >>>>>>> ******************************************************************************** >>>>>>> system.make:140: recipe for target 'implementation/system.bit' failed >>>>>>> gmake: *** [implementation/system.bit] Error 1 >>>>>>> ERROR:EDK - >>>>>>> Error while running "gmake -f system.make bits". >>>>>>> >>>>>>> It seems to be a timing constraint. >>>>>>> >>>>>>> How do I deal with this? >>>>>>> >>>>>>> Thanks for the help! >>>>>>> >>>>>>> Heystek >>>>>>> >>>>>>> -- >>>>>>> You received this message because you are subscribed to the Google >>>>>>> Groups "[email protected]" group. >>>>>>> To unsubscribe from this group and stop receiving emails from it, >>>>>>> send an email to [email protected]. >>>>>>> To view this discussion on the web visit >>>>>>> https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CALWRf%3DQBAuUfbk9H%3D7hOS%2BO6epcTe%2BrR7egqKecFMCrf0J9Yqg%40mail.gmail.com >>>>>>> <https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CALWRf%3DQBAuUfbk9H%3D7hOS%2BO6epcTe%2BrR7egqKecFMCrf0J9Yqg%40mail.gmail.com?utm_medium=email&utm_source=footer> >>>>>>> . >>>>>>> >>>>>> >>>>>> -- >>>>>> You received this message because you are subscribed to the Google >>>>>> Groups "[email protected]" group. >>>>>> To unsubscribe from this group and stop receiving emails from it, >>>>>> send an email to [email protected]. >>>>>> To view this discussion on the web visit >>>>>> https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CAG67D36TnqUAXAufGUtsAqBCry0VMk%2BKxp%2BsHicvOu9kVsG5Aw%40mail.gmail.com >>>>>> <https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CAG67D36TnqUAXAufGUtsAqBCry0VMk%2BKxp%2BsHicvOu9kVsG5Aw%40mail.gmail.com?utm_medium=email&utm_source=footer> >>>>>> . >>>>>> >>>>> >>>>> >>>>> -- >>>>> You received this message because you are subscribed to the Google >>>>> Groups "[email protected]" group. >>>>> To unsubscribe from this group and stop receiving emails from it, send >>>>> an email to [email protected]. >>>>> To view this discussion on the web visit >>>>> https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CADY26KBGfRM%2BDO0VXygJM975Fj_OmJdpZyy8Dsc-hREw75sbpg%40mail.gmail.com >>>>> <https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CADY26KBGfRM%2BDO0VXygJM975Fj_OmJdpZyy8Dsc-hREw75sbpg%40mail.gmail.com?utm_medium=email&utm_source=footer> >>>>> . >>>>> >>>>> >>>>> >>>>> -- >>>>> You received this message because you are subscribed to the Google >>>>> Groups "[email protected]" group. >>>>> To unsubscribe from this group and stop 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