Hello Casperites, I know that the DRAM block in the ROACH2 is itself a trouble. I have tried to make a model using the blocks in the casper-astro github but I couldn't get any response of the block.
In some thread of the mailing list I found the repo of the SMA where I could use the DRAM without the PPC interface, but only works using the addresses in the range (0-2^24) so using this implementation we could use 603MB of the DRAM. https://github.com/Smithsonian/mlib_devel Our ROACH2 has a m393b5773 memory stick, reading the datasheet it says that this module has 3 banks, 15 rows and 10 columns. Poking around in the pcores/ddr3_controller/hdl/verilog/ddr3_controller.v I found that configuration has the same default parameters I mention. But after compiled a model I look at the XPS_ROACH2_base/hdl/system_ddr3_controller.v and I found that the row address is now 14... So in some stage of the compilation the parameter is re written. There is a reason for that, or it is just a bug? If its the second one, there is any recommendation to where start to look at? I dont think that its made by other hdl instantiation because in the ddr3_conotrller file the 14 value is written using a number and not a parameter. My main suspect is some matlab oop. -- You received this message because you are subscribed to the Google Groups "[email protected]" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/486133a4-67a6-4420-9df5-0c5afe9b5128n%40lists.berkeley.edu.
