Here are the files that Mike kindly share, in case someone in the future is
looking for a DRAM with ppc interface.
https://drive.google.com/file/d/1sdp1kHDDB5wNqE2S14-5lguI5oUv0kL3/view?usp=sharing

By the way setting the row address in 15 indeed allows me to access 1.2GB
of the DRAM, now I think the default values are set thinking to support 1GB
dram option also.


El sáb., 5 sept. 2020 a las 3:03, Mike Movius (<[email protected]>)
escribió:

>
> Hi Sebastian,
>
> A couple of years ago I managed to get the ddr3 working in a design with a
> PPC interface to read the memory. I think the design was based on the
> ska-sa mlib-devel repo and only caters for firmware read/write. We modified
> the roach1 dram controller to get the ppc interface to work. You (or any
> casperite for that matter) may contact me directly for the yellow block
> files. Regards, MM.
>
>
> ________________________________
> From: Sebastian Antonio Jorquera Tapia <[email protected]>
> Sent: Friday, 04 September 2020 9:57:18 PM
> To: [email protected]
> Subject: Re: [casper] ROACH2 DRAM parameters
>
> After writing this I think I found it, it was the ddr3_controller.mpd file
> which overwrites the parameters. I am going to check if now I have more
> allowable addresses.
>
>
> El vie., 4 sept. 2020 a las 15:08, Sebastian Antonio Jorquera Tapia (<
> [email protected]<mailto:[email protected]>>)
> escribió:
>
> Hello Casperites,
> I know that the DRAM block in the ROACH2 is itself a trouble. I have tried
> to make a model using the blocks in the casper-astro github but I couldn't
> get any response of the block.
>
> In some thread of the mailing list I found the repo of the SMA where I
> could use the DRAM without the PPC interface, but only works using the
> addresses in the range (0-2^24) so using this implementation we could use
> 603MB of the DRAM.
> https://github.com/Smithsonian/mlib_devel<
> https://github.com/Smithsonian/mlib_devel>
>
> Our ROACH2 has a m393b5773 memory stick, reading the datasheet it says
> that this module has 3 banks, 15 rows and 10 columns. Poking around in the
> pcores/ddr3_controller/hdl/verilog/ddr3_controller.v I found that
> configuration has the same default parameters I mention.
> But after compiled a model I look at the
> XPS_ROACH2_base/hdl/system_ddr3_controller.v and I found that the row
> address is now 14... So in some stage of the compilation the parameter is
> re written.
>
> There is a reason for that, or it is just a bug? If its the second one,
> there is any recommendation to where start to look at?
> I dont think that its made by other hdl instantiation because in the
> ddr3_conotrller file the 14 value is written using a number and not a
> parameter. My main suspect is some matlab oop.
>
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