Hi Jeb,

At the beginning of the test, I had the cpu hanging issue.
I followed the instructions here, and fixed the issue:
https://discuss.pynq.io/t/problem-with-using-integrated-logic-analyzer-ila-for-debugging-with-pynq/435/4

Then I downloaded the bit file via JTAG, the PS part didn't hang until I
was trying to read/write PL registers,
so I think it's not caused by cpu_idle.

Did you try to read/write PL registers after you download the bit file via
JTAG?
If so, can you please tell me how you did it?

Thanks!
Best,
Wei



On Mon, Nov 2, 2020 at 6:14 PM Jeb Bailey <[email protected]> wrote:

> Hi Wei,
>    Is there any chance this workaround is related to needing cpu.idle=1 on
> your kernel command line? I know trying to use the system ilas will cause
> the PS side to hang without it.
>
> -Jeb
>
> Sent from my mobile.
>
> On Nov 2, 2020, at 15:57, Wei Liu <[email protected]> wrote:
>
> 
> Hi Casperites,
>
> I'm working on porting casper toolflow on ZCU111.
> I want to share some debugging experiences, which may be helpful.
>
> We have PYNQ image running on the PS part, which is based on Ubuntu18.04.
>
> I found PL registers can't be accessed after the bit file is downloaded
> via JTAG.
> Because PYNQ image is running, SDK can't be used for debugging and no elf
> file is associated,
> which causes some initialization unfinished.
>
> What I did is download the bit file via JTAG first, so we have the GUI for
> debugging.
> Then I downloaded the same bit file via Overlay class from PYNQ, which can
> finish the necessary initialization.
> After that, I can monitor signals from the vivado hardware manager, and I
> can also read or write PL registers.
>
> Hope this will be helpful for debugging on MPSOC with PYNQ image.
>
> Best,
> Wei
>
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