Hey Jack, A little late here but better late than never I suppose...
Papers worth a read: - https://sutherland-hdl.com/papers/2013-SNUG-SV_Synthesizable-SystemVerilog_paper.pdf - http://www.sunburst-design.com/papers/CummingsSNUG2003SJ_SystemVerilogFSM.pdf - https://sutherland-hdl.com/papers/2007-SNUG-SanJose_gotcha_again_paper.pdf Colleagues also recommended these Sutherland textbooks (https://www.sutherland-hdl.com/books_and_guides.html): - RTL Modeling with SystemVerilog For Simulation and Synthesis - SystemVerilog For Design (2nd edition) Cheers, Brian On Friday, April 30, 2021 at 4:05:55 AM UTC-7 jackh...@gmail.com wrote: > Hi CASPERites, > > Does anyone have any resources for learning System Verilog they've used > and particularly like? > > Cheers > Jack > -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe from this group and stop receiving emails from it, send an email to casper+unsubscr...@lists.berkeley.edu. To view this discussion on the web visit https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/78e8c000-0ec2-4701-a7bd-6e04171a06b5n%40lists.berkeley.edu.
