Hi Nitika

The only other thing is possibly to test on a 10 bit red pitaya board
because this is where the functionality was tested on (from my side). Other
test environments that worked (if that might help) would be Vivado 2019.1
and Matlab R2018a.

I would be interested to perform the tests again from my side but I will
only have access to the boards in about three weeks. If you don't get it
right by then, I will get 'on board' with you :)

Thanks
Mathews






On Fri, Feb 11, 2022 at 2:55 AM Yadlapalli, Nitika <[email protected]>
wrote:

> Hi Mathews!
>
> thanks for your response! The files you suggested I look for do exist, I
> verified that the IP clock was selected as sys_clk and I compiled my model
> using this mlib_devel repo you suggested: https://github.com/casper
> -astro/mlib_devel/ <https://github.com/casper-astro/mlib_devel/>
>
> Unfortunately, still no luck 🙁
>
> In a simple model that just takes the ADC input and outputs it on the DAC,
> I'm able to verify that the signal is being sampled and then output again
> correctly with an oscilloscope. Given that this is working, it's confusing
> to me that the estimates for the fpga clock are so incorrect. I suspect
> something in the sys clock counter is going awry? I also wonder if it's
> something related to the fact that I'm using the 14 bit Red Pitaya. I made
> sure the hardware platform is set to “RED_PITAYA_14:xc7z010” but is there
> anything else I should be careful about?
>
>
> Best,
> Nitika
> ------------------------------
> *From:* Mathews Chirindo <[email protected]>
> *Sent:* Wednesday, February 9, 2022 11:03 PM
> *To:* [email protected] <[email protected]>
> *Subject:* Re: [casper] Re: Red Pitaya programming/clocking issue?
>
> Hi Nikita
>
> The estimate_fpga_clock() functionality is based on the implementation of
> the sys_block_counter instance in
> ../mlib_devel/jasper_library/yellow_blocks/sys_block.py and ../
> mlib_devel/jasper_library/hdl_sources/sys_block/sys_block_counter.v.
> Kindly check if these implementations exist in the mlib_devel repository
> you are using. Else, try to test using h <http://goog_10357047>
> ttps://github.com/casper-astro/mlib_devel/
> <https://github.com/casper-astro/mlib_devel/> or
> https://github.com/ska-sa/mlib_devel/
>
> Also the functionality seems to have been tested while the IP clock source
> was selected as sys_clk in the RED_PITAYA platform block in Simulink.
>
> I hope that helps.
>
> KInd Regards
> Mathews
>
>
>
> On Thu, Feb 10, 2022 at 12:26 AM Yadlapalli, Nitika <[email protected]>
> wrote:
>
> Hi Jeff!
>
> Appreciate the response! Adding this line to etc/hosts fixed the issue
> with uploading .fpg files to the red_pitaya.
>
> I reinstalled casperfpga in the way you outlined, and the line last of the
> install reads "Finished processing dependencies for
> casperfpga==0.4.4.dev932+master.eac2d46", so it seems like now I have
> version 0.4.4. I am still having issues with the estimate_fpga_clock()
> function, however. It continues to read randomly changing values, all much
> higher than the 125 MHz I am expecting. Do you have any other suggestions
> for what might be wrong?
>
> Best,
> Nitika
>
> ------------------------------
> *From:* 'Kobesky, Jeffrey CIV USN NRL (5555) Washington DC (USA)' via
> [email protected] <[email protected]>
> *Sent:* Wednesday, February 2, 2022 2:12 PM
> *To:* [email protected] <[email protected]>
> *Subject:* [casper] RE: Red Pitaya programming/clocking issue?
>
>
> Hello Nitika,
>
>
>
> I’m not using conda environment so I can’t comment on that,  but:
>
>
>
> 1.  To clear the “Odd?” problem I ssh’d into red pitaya and added
> “127.0.0.1 localhost” line to etc/hosts on red pitaya.
>
>
>
> 3.  To clear the “value seems to also be varying rapidly rather than
> incrementing steadily as expected” problem I updated casperfpga from
> version 0.1.1 to 0.4.4.  This can be done by doing:
>
>
>
> ~/casperfpga$ sudo pip install -r requirements
>
> ~/casperfpga$ sudo pip install .
>
>
>
> instead of:
>
>
>
> ~/casperfpga$ sudo pip install -r requirements
>
> ~/casperfpga$ sudo pip install casperfpga
>
>
>
> i.e., doing it the first way installs from the local repo instead of the
> remote repo which I think contains an outdate version of casperfpga.  You
> can verify your version is ipython by:
>
>
>
> In[x] casperfpga.--version--   (not sure I have the syntax exactly right)
>
>
>
> Hope that helps -- Jeff
>
>
>
> [image: cid:[email protected]]
>
> *Jeffrey Kobesky *
>
> Electronics Engineer
>
> Naval Research Laboratory
>
> Information Technology Division Code 5555
>
> Bldg 1   Room 222
>
> 4555 Overlook Ave SW
>
> Washington, DC  20375
>
> Office 202.404.7109    Mobile 443.243.1554
>
> [email protected]
>
>
>
>
>
> *From:* Yadlapalli, Nitika <[email protected]>
> *Sent:* Tuesday, January 25, 2022 6:34 PM
> *To:* [email protected]
> *Subject:* [casper] Red Pitaya programming/clocking issue?
>
>
>
> Hi all!
>
>
>
> I am getting started with casper on a Red Pitaya 125-14. I've been
> following the tutorial about using the ADC/DAC boards (
> https://casper-toolflow.readthedocs.io/projects/tutorials/en/latest/tutorials/redpitaya/tut_adc_dac.html)
> and have run into a few issues:
>
>
>
>    1. I'm not able to use upload the upload_to_ram_and_program method
>    with the .fpg file. I get this "ERROR:10.42.0.69:10.42.0.69: no
>    programming informs yet. Odd?" ​and I don't seem to be able to
>    activate the tcpborphserver on the red pitaya either to fix it as I've seen
>    in a previous archive thread.
>    2.
>
>    3. I can use the .bof file for programming the red pitaya, so I've
>    been moving forward with that. If I try to get the clock speed, however,
>    using estimate_fpga_clock(), the output estimated clock speed changes
>    wildly with time and is never consistent with the 125 MHz speed I expect.
>    Additionally, if I try to read the adc_samp_cnts register as outlined in
>    the tutorial, the value seems to also be varying rapidly rather than
>    incrementing steadily as expected.
>
>
>
> Has anyone encountered these issues before? I have all the packages
> installed in a conda environment.
>
>
>
>
>
> Best,
>
> Nitika
>
>
>
> Nitika Yadlapalli (she/hers)
>
> PhD Candidate | Astronomy
>
> California Institute of Technology
>
>
>
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  • ... Yadlapalli, Nitika
    • ... 'Kobesky, Jeffrey CIV USN NRL (5555) Washington DC (USA)' via [email protected]
      • ... Adam Isaacson
      • ... Yadlapalli, Nitika
        • ... Mathews Chirindo
          • ... Mathews Chirindo
          • ... Yadlapalli, Nitika
            • ... Mathews Chirindo

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