Hi Morag, Thanks for quick reply.
Unfortunately, I am unable to work out using your suggestions. My design file is showing output of Simulink scope, but I am unable to get anything out of RP-DAC. I am able to create a System Generator IP catalog and include the design as IP core in an existing Red Pitaya Vivado project and it seem to work there, but with casper, same design doesn't work. Another question is how to write non integer values. I am using write() function with binary equivalent of the number configured using '' in python like dat = '10000000000000000000' for 0x800000 corresponding to 3.90625 MHz output. I am also attaching my simulink files for your reference. For simplicity, I have configured dds with fixed phase increment. One file is a simple Sys Gen file where I export the design as IP catalog and it is working. dds_example.slx Other file is Casper design. dds_example_red_pitaya.slx My system configuration is: Vivado 2019.1.3 Matlab 2018a I hope you can help here by correcting any mistakes that I may have done. Thank you - Ashish From: "Morag Brown" <[email protected]> To: "casper" <[email protected]> Sent: Friday, June 17, 2022 2:04:46 PM Subject: Re: [casper] Problems in integration of DDS and Cordic Compilers with CASPER toolflow with Red Pitaya Hi Ashish, So I had some luck playing around with the Xilinx DDS compiler block a few years ago. I must admit my memory on the topic is quite fuzzy and I never really quite figured out how it all works, but I did manage to get an output. I'm assuming that you aren't seeing an output from the block in simulation? I configured the design I had working (see attached image) to match your specifications, and it rather frustratingly works for me. The only difference I can see is that I either have the explicit period unchecked, or have it set to 1 (both work for me). But setting it to 8e-9 results in no output. Do you have a gateway out/to processor software register on the output going to the scope? I find that sometimes just connecting Xilinx blocks to a simulink display results in some weirdness. Also, what version of Matlab are you using? My design was created in R2019a, so there could be some difference if you're using R2018a for the Red Pitaya toolflow. If you are on 2018a, then I'll be happy to try things out on that version myself. As far as writing values to software registers goes once you have it on hardware, the intro CASPER tutorials (which can be found [ https://casper-toolflow.readthedocs.io/projects/tutorials/en/latest/tutorials/redpitaya/tut_intro.html | here ] for the RP) give details on how to do this. I can't speak to the CASPER DDS blocks, unfortunately. Morag On Thu, Jun 16, 2022 at 4:10 PM Ashish Sharma < [ mailto:[email protected] | [email protected] ] > wrote: Hi, I am trying to use CASPER toolflow for my development work on Red Pitaya STEMLAB 125-14 board. I wish to use DDS and Cordic Compilers in System Generator Environment but I am not able to see any output from DDS. My settings are as follows: Configuration Options : Phase_Generator_and_SIN_COS_LUT System Clock (MHz) : 125 Number of Channels : 1 Parameter Selection: Hardware_Parameters Noise Shaping : None Phase Width : 32 Output Width : 14 Use Explicit period: CHECKED Explicit Period: 8e-9 Phase Increment Programmability : Programmable I wish to generate a 3.90625 MHz sine wave out from DDS and feed it to Red Pitaya DAC channel 1. So the Phase increment value is computed in ufix_32_32 as = (3.90625/125)*2^32 config_tvalid port of DDS is connected to XSG Constant block with boolean value 1 config_tdata_pinc of DDS connection is tried in 3 ways: 1. using a xilinx constant with a value = 0.03125 and configured as ufix_32_32 2. using a simulink constant with value = 0.03125 which is connected to a software register with "From Processor" setup and configured as ufix_32_32. I am not sure, how to send it a value using rp.write() function. 3. using a simulink constant with value = 0.03125 which is connected to a software register with "From Processor" setup and configured as ufix_32_0 i.e. as integer, followed by a Right Shift operator by 32 and output format as ufix_32_32. This is done so that I can pass a value to software register by using rp.write_int() function. In the simulink model I have tried with Simulink System Period (sec) = 1 as well as 8e-9 But no setting is helping me to observe a sine wave signal from DAC output. Please help in identifying an issue with my design settings. Also let me know, is it possible to use DDS, and SINCOS blocks from CASPER XPS toolset in simulink? If yes then how to set it up? Any help will be highly appreciable. Thank you. -- Ashish Sharma Inter-University Accelerator Centre, India -- You received this message because you are subscribed to the Google Groups " [ mailto:[email protected] | [email protected] ] " group. To unsubscribe from this group and stop receiving emails from it, send an email to [ mailto:[email protected] | [email protected] ] . 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dds_example_red_pitaya.slx
Description: Zip archive
dds_example.slx
Description: Zip archive
