Hi Sebastian, I have an app that I'd like to port to the RFSoC4x2 that might help -- when I can get some help porting it.
It currently works on several boards including the ZCU208, which has the same clock chips as the RFSoC4x2. The app allows you to set the ADC clocks to almost any desirable frequency between 100MHz and over 5GHz (it prints a warning when you ask to exceed the ADC spec). When you tell it to set a frequency, the LMK and LMX register settings are printed in the serial debug output, so you could copy them from that. The app is also useful as an oscilloscope, spectrum analyzer, and for analyzing transfer functions. I'd like to make it available for free to academic users. This will give my business some publicity. I don't have an RFSoC4x2 board, so I can't port it on my own. I have an offer to help port it in a few months. If anyone has a board and some time and wants to help me port it earlier, please get in touch. Regards, Ross On Wed, Jun 14, 2023, 12:03 PM Sebastian Antonio Jorquera Tapia < [email protected]> wrote: > Hi, I want to change the sampling rate of the ADCs programing the LMX and > LMK but I have some doubts about how the clocking scheme is done. > > The clocking diagram in the RFSoC4x2 reference manual shows that the LMK > has one output of 122.88MHz that goes to the pin AN11, another clock of > 245.76 goes to the LMX which produces the 491.52MHz that goes to the > ADC-DAC tiles. > > On the other hand in the simulink project I have several clocks that I > would like to understand. > In the RFDC block I can set the sampling rate, output clock and reference > clock. The reference clock should be the one that comes from the LMX and > the output clock is the frequency of the ADC data. > In the XSG block I can set the user ip clock and the rfpll clock, checking > the generated vivado files the rfpll clock is the 122.88MHz clock from the > LMK and goes to a MMCME to generate the user ip clock and this clock is the > one used as the main clock of the design. > > As a summary what I understand until now is: > -RFDC clocks: > -reference clock: Comes from the LMX, that is being feed by one signal > of the LMK. > -Sampling rate: generated by the internal pll of the RFDC > -output clock: output data clock signal > -XSG clocks: > -RFPLL clock: comes from one output of the LMK. > -user ip clock: MCMME output clock generated using RFPLL clock as the > input clock. > its also the main clock of the simulink > model. > > I didnt found a FIFO or some sort of cdc to pass from the rfdc output > clock to the user ip clock, does this means that I need to select carefully > the LMK output for the REFPLL in order to match the clock generated by the > LMX (RFDC refence clock), or can I trust that the clock generated by the > MCMME will just work? > > I am missing something? > > -- > You received this message because you are subscribed to the Google Groups " > [email protected]" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to [email protected]. > To view this discussion on the web visit > https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/0d750b1f-0c12-4d67-85bb-29c14759c964n%40lists.berkeley.edu > <https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/0d750b1f-0c12-4d67-85bb-29c14759c964n%40lists.berkeley.edu?utm_medium=email&utm_source=footer> > . > -- You received this message because you are subscribed to the Google Groups "[email protected]" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CAG4nf702fQe3u2H2wRUt%2BXu2v-0jVUy4edoHnSNPoq0vKY0WnQ%40mail.gmail.com.
