Hi Sebastian, I wanted to close the loop on this one, since I started out with the same questions and it didn't seem like you received an answer. I think you more or less have the correct understanding of how each of the clocks are derived, but to reiterate:
-The ADC clock rate (i.e. the sample rate), is derived from the reference clock supplied by the LMX2594 to the RF data converter, the frequency of which is what you enter into the "Reference Clock" field of the RFDC Casper block. Assuming you have "Enable Tile PLLs" checked in the RFDC block, the PLL internal to the RF data converter is responsible for this. -The user clock rate is derived from the PL reference clock supplied by the LMK04828 to the FPGA fabric, the frequency of which is what you enter into the "RFPLL PL Clock Rate" field in the RFSoC4x2 XSG block. The PLL associated with the FPGA's MMCM is responsible for this. -The output clock is used for clock forwarding from one ADC tile to another, although I believe this is currently not implemented for the Casper RFDC block What clock rates one can obtain for each of these are constrained by the dividers and VCOs internal to each of the corresponding PLLs. For the RF data converter, these can be found here: https://docs.amd.com/r/en-US/pg269-rf-data-converter/PLL-Parameters Whereas for the MMCM, the constraints can be found here: https://docs.amd.com/r/en-US/ug572-ultrascale-clocking/MMCM-Attributes There is also the further constraint that your user clock must match the required AXI4 stream clock, which is equal to: User clock = AXI4 stream clock = Sample rate / Decimation / Number of AXI4 stream samples per user clock The Casper RFDC block will automatically compute this for you when you enter something into the "Sampling Rate" field. It will also automatically compute the ADC reference clock, but interestingly the PLL constraints it assumes aren't quite the same as what's specified in the ADC documentation above, and ultimately the reference clock it gives you will result in a sample rate that doesn't quite match up with the one you specify in the Sampling Rate field and is incompatible with the required AXI4 stream clock shown (have a close look at calc_refclk.m in the casper-astro/mlib_devel repo). Similarly, the jasper backend will mis-configure the MMCM if you do not specify a user clock rate that is compatible with the constraints of the corresponding PLL (see clk_factors.py in casper-astro/mlib_devel/jasper_library, it will only give the closest frequency to what you specify). For this reason, I do not rely on the RFDC block to guide me to the correct clock frequencies. In practice what I do is I start with PL reference and ADC reference clocks supplied by the LMK04828 and LMX2594 (e.g. 122.88 and 491.52 MHz in the default Casper config files), and use the above PLL constraints to work forwards and calculate all possible sample rates I can use given those clock rates and my required decimation and AXI4 stream sample number. If desired, I can send along a handy Python script that does this. -Walter -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe from this group and stop receiving emails from it, send an email to casper+unsubscr...@lists.berkeley.edu. To view this discussion visit https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/PH7PR14MB5368930D7E91BE73519BEF6EACB72%40PH7PR14MB5368.namprd14.prod.outlook.com.
