Dear Adam,

Thank you for the response.  My fpg bitstream file was downloaded 
incorrectly and was corrupted.   A helpful change here would be to include 
MD5 digests alongside them.    More thoroughly, have python check the MD5 
prior to attempting to load them. 

On Friday, July 14, 2023 at 9:53:45 AM UTC-4 Adam Isaacson wrote:

> Hi Ken,
>
> This is normally stored in the yaml file in your 
> mlib_devel/jasper_library/platforms/zcu216.yaml file - see attached png 
> image. The RFSoC device that I have in a repo with Matlab R2018a is: 
> xczu49dr-ffvf1760-2-e-es1, but it may be a production device in the latest 
> mlib_develrepo, not sure. It depends whether Xilinx made production silicon 
> for this FPGA or left it as an engineering sample.
>
> Kind regards,
>
> Adam
>
> On Fri, Jul 14, 2023 at 3:13 AM Ken Semanov <[email protected]> wrote:
>
>> I attempted to retrieve the exact chip used in the FPGA here, but  this 
>> casperized image does not contain  lspci,  lshw, nor even hwinfo.    I 
>> sniffed around /sys/bus  for an hour and got nowhere.  Anyone know where 
>> the FPGA information is hiding? 
>>
> On Thursday, July 13, 2023 at 8:20:07 PM UTC-4 Ken Semanov wrote:
>>
> I am attempting to load the bitstream `zcu216_tut_spec.fpg`  located here,
>>>
>>>
>>> https://github.com/casper-astro/tutorials_devel/tree/main/rfsoc/tut_spec/prebuilt/zcu216
>>>
>>> The call to `fpga.upload_to_ram_and_program()` causes  
>>> transport_katcp.py:654  to invoke an exception ,
>>>
>>>      RuntimeError: 132.177.x.x: no programming informs yet. Odd?
>>>
>>> I have been sending bitstreams to the board all afternoon with no 
>>> problems like this, so this is likely a problem with the fpg file.  
>>> However,  here is some more information.
>>>
>>> In [5]: casperfpga.__version__
>>> Out[5]: '0.4.4.dev1336+py38.276ee44'
>>>
>>> root@dhcp-132-177-143-xxx:/home/casper# more /etc/hosts
>>> 127.0.0.1 localhost
>>> ::1 localhoot6.localdomain6 localhost6
>>>
>>> root@dhcp-132-177-143-xxx:/home/casper# ping -c 2 localhost
>>> PING localhost (127.0.0.1) 56(84) bytes of data.
>>>
>> 64 bytes from localhost (127.0.0.1: icmp_seq=1 ttl=64 time=0.061 ms
>>> 64 bytes from localhost (127.0.0.1: icmp_seq=2 ttl=64 time=0.040 ms
>>>
>>
>>> --- localhost ping statistics ---
>>> 2 packets transmitted, 2 received, 0% packet loss, time 1016ms
>>> rtt min/avg/max/mdev = 0.040/0.050/0.061/0.010 ms
>>>
>>> root@dhcp-132-177-143-xxx:/home/casper# ps aux | grep tcpbo
>>> root         495  0.0  0.0   3824  2440 ?        Ss   15:37   0:00 
>>> /bin/tcpborphserver3 -b /lib/firmware
>>> root         732  0.0  0.0   5964   644 ttyPS0   S+   16:01   0:00 grep 
>>> --color=auto tcpbo
>>>
>>>
>>>         upload_thread.join()  # wait for the file upload to complete
>>>         upload_result = upload_queue.get()
>>>         if upload_result != '':
>>>             raise RuntimeError('upload(%s)' % upload_result)
>>>         # wait for the '#fpga ready' inform
>>>         done = False
>>>         while not done:
>>>             try:
>>>                 inf = unhandled_informs_queue.get(block=True, 
>>> timeout=timeout)
>>>             except queue.Empty:
>>>                 self.logger.error('%s: no programming informs yet. Odd?' 
>>> % self.host)
>>>                 raise RuntimeError('%s: no programming informs yet. '
>>>                                    'Odd?' % self.host)
>>>             if (inf.name == 'fpga') and (inf.arguments[0].decode() == 
>>> 'ready'):
>>>                 done = True
>>>         self.logger.info('%s: programming done.' % self.host)
>>>         self.unhandled_inform_handler = None
>>>         self._timeout = old_timeout
>>>         self.prog_info['last_programmed'] = filename
>>>         self.prog_info['last_uploaded'] = filename
>>>         return True
>>>
>>>
>>>
>>> -- 
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