Hi Ken, I am glad you sorted your issue out in the end and thanks for the how to and suggestions on the MD5 checksum. These are always useful. I have never physically worked with the ZCU216 myself, but I have worked with other FPGAs.
The yaml file FPGA description is a useful way to determine the FPGA without compiling the design or using the hardware. The developers created this file knowing which FPGA is required, so this is a reliable source. However, once the design is compiled then the user can always open the myproj Vivado project and determine the FPGA type that way - that should be the easiest. Therefore, you just compile the slx in the tooflow and it will generate a "myproj", which is the Vivado FPGA project (myproj.xpr) under /jasper_library/test_models/<slx name>/myproj or the directory you work with. There should also be a "gogogo.tcl" file that has the FPGA type in it based on what was in the yaml file. Vivado sources this file and then creates the project based on the contents of "gogogo.tcl" generated by the CASPER Toolflow located under "/jasper_library/test_models/<slx name> directory. I would look at the following documentation folders provided by CASPER to make your life easier - hopefully :): 1) Runnng the Toolflow: https://casper-toolflow.readthedocs.io/en/latest/src/Running-the-Toolflow.html 2) CASPER toolflow (general): https://casper-toolflow.readthedocs.io/en/latest/ 3) General CASPER website: https://casper.berkeley.edu/ There are also slack groups ( https://join.slack.com/t/casper-astro/shared_invite/zt-1z3sl5sh3-M6lZi3Idn2kGVx0BFs7yIA) where you can get assistance on the various channels - there is definitely an RFSoC channel. Maybe you know all of this already, but if not then there is some more info for you to digest. CASPER is a collaboration, so if you would like CASPER to make certain changes you feel would benefit the community then you are welcome to fork a repo, make the changes and do a pull request. I can't promise you that CASPER will incorporate them, but they will be reviewed and considered. I would suggest that you join the developers email if you want to get involved with this: casper-dev+subscr...@lists.berkeley.edu. There is also the 2023 CASPER conference coming up in Florida that you can attend if you wish to understand more about the toolflow. There will be people on hand and tutorial sessions, which are always useful - https://casper.astro.berkeley.edu/workshop2023/. Kind regards, Adam On Sat, Jul 15, 2023 at 1:55 AM Ken Semanov <shapkiqua...@gmail.com> wrote: > Hello Adam,Here is a method for determining the FPGA part number on a > ZCU216.1) Connect the ZCU216 to a network switch or router by its RJ45 > ethernet, and boot it into an SD card. Connect a computer to the same > network, and install Vivado. 2) In Vivado , menus `Flow >> > Op > > > > > > > > > > > > > > > > > > > > > > > > > > > <https://za.report.cybergraph.mimecast.com/alert-details/?dep=qmx%2Fn%2FiZdMMoBIefbJFGMg%3D%3D4qKZgaAlbL%2FIzYgEJI9UCYf1R2RaqDFNdM43CHo%2FbUKrV7YDIos0uu1efS6jD9WPzWgsV5GpmDHyQAUuj9XNI2h0iqK2lwL3KOrSWK1QjviRTzn1jDEPs0xgpORrA0NTD6W4UheovF9UANgfpR9UyHEDTVTuCluQ0cSC1Z1WW07AP%2F5iJskDiMESQtMSFbNmXJ9Lvm%2BSZcokqD3HBprerVkQls0tUq35Qj%2BjxAHb46J0vscFOJIRnri17tBfr6TmTiFdfazH346GkTVMQ5OZMEgIcdmpmqMhUIV3gFd%2BcJXLdDhuWibN9DFvCz6fjT48qPU2gMIVZ06Fx9at9Trtpm0OZXIJuNCTHujEXV%2FORU8wA7avN96N4s%2Fv5J7D2rBIbJfdWdC2SFQQZ2sR3K4VRl0ECBf006eRSglD8u%2B8BROZ%2BM4iDdfyb%2BEA%2BKWkPVCv4BYU%2BOZlxJvewhg%2B%2F8QKtt6r%2B7TF%2FA7awasEAMXP1Mx3yAY4hE%2BDDuugCL9z7JO129uosVC0mexRH8HYR4wSQ%2FVLSbrtTPj%2B7pYw57lCE%2BnidPhaIG9HbQDbik1RhRESP7mWfZTAsJcvptODvoSH%2BuCSaNTmbihtv6zX2jm94sZyVtJZPiJ7hjYq5I6RmesF2RI2Kq6tNEgnW5wMRFlUWiQZnQhZ7fbTPrUYtfzIR5aPqs7DV%2B6P2ITwXejWb2W63ND06gCcsZBDfq7h16D4UoCrMYhKA72oQQPmd8neOx3Qd1mvQ3LsR2xtR6tsfk9e7QlmmpnajURGrrPSd2OvWQ%3D%3D> > Hello Adam, > > Here is a method for determining the FPGA part number on a ZCU216. > > 1) Connect the ZCU216 to a network switch or router by its RJ45 ethernet, > and boot it into an SD card. Connect a computer to the same network, and > install Vivado. > > 2) In Vivado , menus `Flow >> Open Hardware Manager` > > 3) Click `Open Target >> Open New Target..` > > 4) Next >> Next > > 5) Set "Connect To" to `Local server` . `Next` > > 6) Click on the items on the list until the `Hardware Devices` table is > populated by stuff. > > 7) Select the item within the `Hardware Devices` table that is *not *arm*** > . What you have selected will turn blue. > > 8) Press `Next` Press `Finish` > > 9) A form on the left middle will be `Hardware Device Properties` , listed > there is `Part:`. That is your FPGA. > > Mine reads xczu49dr > > > On Friday, July 14, 2023 at 9:53:45 AM UTC-4 Adam Isaacson wrote: > >> Hi Ken, >> >> This is normally stored in the yaml file in your >> mlib_devel/jasper_library/platforms/zcu216.yaml file - see attached png >> image. The RFSoC device that I have in a repo with Matlab R2018a is: >> xczu49dr-ffvf1760-2-e-es1, but it may be a production device in the latest >> mlib_develrepo, not sure. It depends whether Xilinx made production silicon >> for this FPGA or left it as an engineering sample. >> >> Kind regards, >> >> Adam >> >> On Fri, Jul 14, 2023 at 3:13 AM Ken Semanov <shapki...@gmail.com> wrote: >> >>> I attempted to retrieve the exact chip used in the FPGA here, but this >>> casperized image does not contain lspci, lshw, nor even hwinfo. I >>> sniffed around /sys/bus for an hour and got nowhere. Anyone know where >>> the FPGA information is hiding? >>> >> On Thursday, July 13, 2023 at 8:20:07 PM UTC-4 Ken Semanov wrote: >>> >> I am attempting to load the bitstream `zcu216_tut_spec.fpg` located here, >>>> >>>> >>>> https://github.com/casper-astro/tutorials_devel/tree/main/rfsoc/tut_spec/prebuilt/zcu216 >>>> <https://github.com/casper-astro/tutorials_devel/tree/main/rfsoc/tut_spec/prebuilt/zcu216> >>>> >>>> The call to `fpga.upload_to_ram_and_program()` causes >>>> transport_katcp.py:654 to invoke an exception , >>>> >>>> RuntimeError: 132.177.x.x: no programming informs yet. Odd? >>>> >>>> I have been sending bitstreams to the board all afternoon with no >>>> problems like this, so this is likely a problem with the fpg file. >>>> However, here is some more information. >>>> >>>> In [5]: casperfpga.__version__ >>>> Out[5]: '0.4.4.dev1336+py38.276ee44' >>>> >>>> root@dhcp-132-177-143-xxx:/home/casper# more /etc/hosts >>>> 127.0.0.1 >>>> <http://127.0.0.1> >>>> localhost >>>> ::1 localhoot6.localdomain6 localhost6 >>>> >>>> root@dhcp-132-177-143-xxx:/home/casper# ping -c 2 localhost >>>> PING localhost (127.0.0.1 >>>> <http://127.0.0.1>) >>>> 56(84) bytes of data. >>>> >>> 64 bytes from localhost (127.0.0.1 >>>> <http://127.0.0.1>: >>>> icmp_seq=1 ttl=64 time=0.061 ms >>>> 64 bytes from localhost (127.0.0.1 >>>> <http://127.0.0.1>: >>>> icmp_seq=2 ttl=64 time=0.040 ms >>>> >>> >>>> --- localhost ping statistics --- >>>> 2 packets transmitted, 2 received, 0% packet loss, time 1016ms >>>> rtt min/avg/max/mdev = 0.040/0.050/0.061/0.010 ms >>>> >>>> root@dhcp-132-177-143-xxx:/home/casper# ps aux | grep tcpbo >>>> root 495 0.0 0.0 3824 2440 ? Ss 15:37 0:00 >>>> /bin/tcpborphserver3 -b /lib/firmware >>>> root 732 0.0 0.0 5964 644 ttyPS0 S+ 16:01 0:00 grep >>>> --color=auto tcpbo >>>> >>>> >>>> upload_thread.join() # wait for the file upload to complete >>>> upload_result = upload_queue.get() >>>> if upload_result != '': >>>> raise RuntimeError('upload(%s)' % upload_result) >>>> # wait for the '#fpga ready' inform >>>> done = False >>>> while not done: >>>> try: >>>> inf = unhandled_informs_queue.get(block=True, >>>> timeout=timeout) >>>> except queue.Empty: >>>> self.logger.error('%s: no programming informs yet. >>>> Odd?' % self.host) >>>> raise RuntimeError('%s: no programming informs yet. ' >>>> 'Odd?' % self.host) >>>> if (inf.name >>>> <http://inf.name> >>>> == 'fpga') and (inf.arguments[0].decode() == 'ready'): >>>> done = True >>>> self.logger.info >>>> <http://self.logger.info>('%s: >>>> programming done.' % self.host) >>>> self.unhandled_inform_handler = None >>>> self._timeout = old_timeout >>>> self.prog_info['last_programmed'] = filename >>>> self.prog_info['last_uploaded'] = filename >>>> return True >>>> >>>> >>>> >>>> -- >>> You received this message because you are subscribed to the Google >>> Groups " >>> http://cas...@lists.berkeley.edu"; >>> group. >>> To unsubscribe from this group and stop receiving emails from it, send >>> an email to casper+un...@lists.berkeley.edu. >>> To view this discussion on the web visit >>> https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/492272fe-ffef-4dc6-a3d0-d61ae18c9a94n%40lists.berkeley.edu >>> <https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/492272fe-ffef-4dc6-a3d0-d61ae18c9a94n%40lists.berkeley.edu?utm_medium=email&utm_source=footer> >>> . >>> >> >> >> >> >> *Disclaimer* >> >> The information contained in this communication from the sender is >> confidential. It is intended solely for use by the recipient and others >> authorized to receive it. If you are not the recipient, you are hereby >> notified that any disclosure, copying, distribution or taking action in >> relation of the contents of this information is strictly prohibited and may >> be unlawful. >> >> This email has been scanned for viruses and malware, and may have been >> automatically archived by Mimecast, a leader in email security and cyber >> resilience. Mimecast integrates email defenses with brand protection, >> security awareness training, web security, compliance and other essential >> capabilities. Mimecast helps protect large and small organizations from >> malicious activity, human error and technology failure; and to lead the >> movement toward building a more resilient world. To find out more, visit >> our website. >> > -- Disclaimer The information contained in this communication from the sender is confidential. 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