Hi Bishnu,
I got your message just after I sent my reply, sorry.
Cheers,
Kaj
On 19.2.2025 3.50, Bishnu Kumar Sharma wrote:
Hi Ken,
This is one of our issues, and I also faced the same problem. When I
checked the mailing list of the CASPER, I found somebody already
reported the problem. Simulink files easily compile with it and you can
get both the .fpg and .dtbo files and then there is no signal in
the design. I have attached the screenshot for you to look over. It is
always wise to check the previous issue raised by Casperites in the
mailing list that is what i usually do.
- This problem persists when you rename the .slx file name. This is
because renaming slx file name doesn't change the port name inside
(mask) the RFDC block. If I create the file supposedly,
bishnu_rfsoc4x2_tut_rfdc_real.slx. Inside rfdc I should get ports name
"rfsoc4x2_tut_rfdc_real_rfdc_m00_axis_tdata" and etc. After changing the
file to bishnu.slx, inside RFDC block the name of ports should be
"bishnu_rfdc_m00_axis_tdata", but it doesn't update the name
automatically, it still is "rfsoc4x2_tut_rfdc_real_rfdc_m00_axis_tdata"
etc. You have to rename the ports inside it manually or remove the old
rfdc and keep the new one from the Simulink library. This technique
works for me, so far. I haven't gone deep inside the source code of
RFDC, this is what i observed. I hope this helps for you. Thank you.
Best Regards
Bishnu Sharma
Institute of Astronomy and Astrophysics
Academia Sinica
On Wed, Feb 19, 2025 at 6:30 AM Ken Semanov <[email protected]
<mailto:[email protected]>> wrote:
Changing the file names of an SLX file can cause LUT errors during
jasper compiles. These errors are fatal and will drop the compile
to command line in Matlab. The CASPER toolflow official
documentation should mention this problem, if -- for no other reason
-- CASPER doesn't have a mechanism to check whether the current SLX
filename has been changed
These LUT errors occur in the later stages of implementation, during
the "Logical Optimization" stages. The blocks in the design which
invoke the missing logic LUT error are random, and seem to be
related to the order in which optimizer selects blocks for
optimizing. For example, if the offending block is removed, the LUT
error will migrate to some other -- often unrelated -- block in a
different portion of the overall design. If that new offending block
is removed, the LUT error migrates to yet another block, and so on
ad infinitum.
We might ask why this occurs. A name-changed SLX survives
completely through the synthesis stage of jasper compile, making the
error unusually pernicious.
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