On Fri, 2017-07-28 at 18:04 +0100, Rob Jarratt via cctalk wrote: > Anyone have any thoughts on whether those data signals look right?
It doesn't look obviously wrong. If the vertical scale is 2V per box then the amplitude is probably about right for 74LS logic. I think you said this was on a shared data bus and the little glitch might well be a benign artifact (either bus turnaround or just a reflection of some internal logic in whatever chip was driving the bus at the time). But it's quite hard to say anything very intelligent about that signal based on just one waveform in isolation. p.
