Hi Paul!
That is really interesting. Did you need to recreate the delay lines or
any of that circuitry, or was it just wire the NAND gates into the chip
address matrix and ignore all the various TP1-TP4 states?
Looking at it I could probably build the basic circuitry on a large
breadboard, I've certainly got the chips from fixing all those M series
boards. That plus a pair of 32k*8 static ram chips from my 386 cache
days and I should be set....
Now where did that big breadboard go?
CZ
On 1/20/2022 3:51 AM, [email protected] wrote:
Not a direct answer Chris, but back in the mid-70's I built a BM8 surrogate the hard
way (we were an impoverished neurophysiology lab so cutting corners wherever
reasonable) using banks of 2102L and S100 RAM PCBs. For density I piggy-backed the
2102's to get 8Kbyte boards, then 3 boards gave 16Kword, so 6 RAM boards were
sufficient to fill out the memory space. The controller was a 1:1 implementation of
the DEC schematic, which (if memory serves) just fit onto a single S100 prototyping
board. Cabling from the 8/L was simple ribbon with alternating grounds. Chassis
was ad hoc using a S100 backplane suitably reinterpreted plus a pair of 8"
fans. Added suitable additional DF/IF switches and lamps to the existing
filler-panel and then attached that to the chassis-front so that it all looked
pretty good. It worked for many years without incident, although AFAIK only core
memory was used for execution; the SRAM was used only for data -- and every added
word was taken advantage of :-}.
So there's an existence proof that what you propose isn't unreasonable. I'd
probably have preferred to have a nice backplane and applicable modules to WW,
but point-to-point wiring on the prototyping board worked. Given my skill-set
at the time it was a rather risky venture, but the ROI was excellent.
Evidently the DEC design was forgiving enough that my recreation worked on the
first try.
If you decide to pursue the FPGA (or something) approach I'd be interested in
doing the same with my current 8/L. If you go that route, might as well build
out all three bits of DF/IF control even if there may not be any accompanying
front-panel.
-----Original Message-----
From: cctalk <[email protected]> On Behalf Of Chris Zach via cctalk
Sent: Wednesday, January 19, 2022 11:08 PM
To: CCTalk mailing list <[email protected]>
Subject: Building a BA08 for a pdp8/L
So now that my pdp8/L is up and running (it now has a serial port and runs
FOCAL69 quite well) I'm thinking about the next step, which is of course more
memory.
This requires a BA08 or BM8/L or something expansion box but to be honest I
have enough spare flip chips and such from the wrecked 8/I to build about 3
core memory systems. So given that the schematics for the
BA08 are online, they look pretty darn simple, I have the parts, and I have the
parts does anyone know if it's possible to get a flip chip backplane to work on
and wire up to emulate a BA08?
It looks like they just used the data break interface lines to hook up to the
processor. Everything's there, Memory address bus, memory data bus, and the
various signals for jumps and the like that could allow one to decode and
implement the extra instructions needed.
Hm. Might just be easier to build it with an FPGA or something as it's mostly
linking up simple gates and the whole core memory section could be removed by a
4k*12 memory array. Anyone ever done this?
C
