Thank you. I _would have_ probably also looked at the analogous "MM8I_Schem_Aug69.pdf" print set. But those were antediluvian times; no Bitsavers and DEC wasn't handing out free print sets. You could purchase them, though -- I still have KA10 and MA10 documentation that I acquired that way for my own education/amusement :->.
Fortunately I had access to the full (32Kw MC8-I) controller hard-copy documentation for the 8/I courtesy of an amazingly built-out system installation in the lab below us (8/I with a full 32Kw core plus a pair of DF32 plus at least two TU56) who was willing to serve as my personal lending-library :->. AFAICS that documentation hasn't been captured in Bitsavers. I have found my 45 y/o 8x11 taped together photocopies if you decide to go past adding a single additional field. Aside from a few annotations there plus some sketched connector-signal information I haven't found any as-built documentation -- not even a IC-laydown -- although I see that I used SSM MB6A boards for the SRAM arrays. Unfortunately no pictures and the system is (very) long gone. WRT the delay lines, I think that you've nailed it -- my lack of recall is likely because none of the special timing requirements for the RMW cycle(s) for core applied so I didn't need to replicate that part of the control; individual R or W cycles based on the 2102L are necessarily more than fast enough. Unfortunately none of my implementation-related notes/sketches appear to have survived :-<. And the few that do are often on the "clean" side of reused paper. Poor church mice ... I did also find documentation for a MONOSTORE V/PLANAR 1K-word to 8K-word SRAM module (pub. 1976) for an 8/E that I suspect that I studied carefully to see how OMNIBUS-based signaling was being handled in an environment where RMW core was also supported. It claims to have used "AMD DS9408" parts according to the inventory; have never heard of that one. In roughly the same time-period I also built-out an AX08 surrogate that went to Appleton, WI, in support of a newly-minted PhD from our lab. I found some notes relating to the necessary control components plus the use of "brick" type A/D and D/A devices. I suspect that the deal was that the new position came with a PO for an 8/I and BA08A (probably w/o memory), but not an AX08 -- so I was looking for the most cost-effective means to replicate critical AX08 functionality ... and did so. It's been a long time. -----Original Message----- From: Chris Zach <[email protected]> Sent: Saturday, January 22, 2022 7:07 PM To: [email protected]; 'General Discussion: On-Topic and Off-Topic Posts' <[email protected]> Subject: Re: Building a BA08 for a pdp8/L There's a couple of MC8/L manuals on bitsavers, this might jog your memory. http://bitsavers.informatik.uni-stuttgart.de/pdf/dec/pdp8/pdp8l/ Anyway, the timing seems to be for the read core, transfer into MB, write back into core (because reads are destructive) then send the completed signal. On MOS memory you probably just need to see the state1 line go high (I have something on the address lines) then just put the data into the MB and go straight to signal 4 (since you don't need to rewrite). On a positive note the 8/L will be able to run as fast as it can as it doesn't have to wait for the core memory. Hm. C On 1/22/2022 11:19 AM, [email protected] wrote: > I have absolutely no idea! Jameco would have likely been my source for most > components although we did have a Hamilton-Avnet in town and it's possible > that ordered some components from them (I still have a NS databook with their > sticker on it). It's entirely possible that I fiddled with some TTL > gate-delays to derive a good-enough approximation. Where are you getting > your circuit schematic from? Maybe if I look at it a bit something will come > back to mind ...
