There's a couple of MC8/L manuals on bitsavers, this might jog your memory.
http://bitsavers.informatik.uni-stuttgart.de/pdf/dec/pdp8/pdp8l/
Anyway, the timing seems to be for the read core, transfer into MB,
write back into core (because reads are destructive) then send the
completed signal. On MOS memory you probably just need to see the state1
line go high (I have something on the address lines) then just put the
data into the MB and go straight to signal 4 (since you don't need to
rewrite).
On a positive note the 8/L will be able to run as fast as it can as it
doesn't have to wait for the core memory. Hm.
C
On 1/22/2022 11:19 AM, [email protected] wrote:
I have absolutely no idea! Jameco would have likely been my source for most
components although we did have a Hamilton-Avnet in town and it's possible that
ordered some components from them (I still have a NS databook with their
sticker on it). It's entirely possible that I fiddled with some TTL
gate-delays to derive a good-enough approximation. Where are you getting your
circuit schematic from? Maybe if I look at it a bit something will come back
to mind ...
