On Tue, Jan 17, 2023 at 10:16:18AM +0000, Peter Coghlan via cctalk wrote: [...] > How about translating code from Z80 which has several registers to 6502 > with rather fewer? That would seem to need some more intelligent thinking > on how to simulate the unavailable registers without causing additional > difficulties.
It is often said that the 6502 has 256 registers, i.e. zero page. So e.g. LD (HL), A could be mechanically transformed into the sequence LDX #0, LDA (h, X), and STA a, with h and a being zero page locations. On the 65C02 the first two operations can be replaced with a simple LDA (h), although it may still be useful to index via X to simulate EXX without performing an expensive copy. As it stands, that replaces a one byte instruction with five byte sequence which is obviously not great, but a relatively simple peephole optimiser can eliminate many of the redundant loads and stores so it wouldn't be quite so bad. After all, one important source of stores is the flags register, which I ignored in the code fragment. A _good_ optimiser can do a lot of clever analysis and transformation, and would probably be needed to handle all of the edge cases well, but would be too large and CPU-intensive to run on a Z80 or 6502 system. It'd be easier to bodge a Z80 into a 6502 machine than try and translate the code. That's what often happened back in the day, after all.
