Hi rnk, hansw,
http://reviews.llvm.org/D4415
Files:
lib/Basic/Targets.cpp
lib/Headers/Intrin.h
lib/Headers/ammintrin.h
lib/Headers/arm_acle.h
lib/Headers/emmintrin.h
lib/Headers/fmaintrin.h
lib/Headers/immintrin.h
lib/Headers/mmintrin.h
lib/Headers/nmmintrin.h
lib/Headers/pmmintrin.h
lib/Headers/smmintrin.h
lib/Headers/tmmintrin.h
lib/Headers/wmmintrin.h
lib/Headers/x86intrin.h
lib/Headers/xmmintrin.h
test/CodeGenCXX/mangle-ms-vector-types.cpp
test/Preprocessor/predefined-macros.c
Index: lib/Basic/Targets.cpp
===================================================================
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -2588,6 +2588,31 @@
/// definitions for this particular subtarget.
void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const {
+ // None of these macros make sense in MSVC compat mode.
+ if (Opts.MicrosoftExt) {
+ if (getTriple().getArch() == llvm::Triple::x86) {
+ switch (SSELevel) {
+ case AVX512F:
+ case AVX2:
+ case AVX:
+ case SSE42:
+ case SSE41:
+ case SSSE3:
+ case SSE3:
+ case SSE2:
+ Builder.defineMacro("_M_IX86_FP", Twine(2));
+ break;
+ case SSE1:
+ Builder.defineMacro("_M_IX86_FP", Twine(1));
+ break;
+ default:
+ Builder.defineMacro("_M_IX86_FP", Twine(0));
+ }
+ }
+
+ return;
+ }
+
// Target identification.
if (getTriple().getArch() == llvm::Triple::x86_64) {
Builder.defineMacro("__amd64__");
@@ -2831,26 +2856,6 @@
break;
}
- if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
- switch (SSELevel) {
- case AVX512F:
- case AVX2:
- case AVX:
- case SSE42:
- case SSE41:
- case SSSE3:
- case SSE3:
- case SSE2:
- Builder.defineMacro("_M_IX86_FP", Twine(2));
- break;
- case SSE1:
- Builder.defineMacro("_M_IX86_FP", Twine(1));
- break;
- default:
- Builder.defineMacro("_M_IX86_FP", Twine(0));
- }
- }
-
// Each case falls through to the previous one here.
switch (MMX3DNowLevel) {
case AMD3DNowAthlon:
@@ -4182,7 +4187,8 @@
: ARMTargetInfo(Triple, false) { }
virtual void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const {
- Builder.defineMacro("__ARMEL__");
+ if (!Opts.MSVCCompat)
+ Builder.defineMacro("__ARMEL__");
ARMTargetInfo::getTargetDefines(Opts, Builder);
}
};
@@ -4193,8 +4199,10 @@
: ARMTargetInfo(Triple, true) { }
virtual void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const {
- Builder.defineMacro("__ARMEB__");
- Builder.defineMacro("__ARM_BIG_ENDIAN");
+ if (!Opts.MSVCCompat) {
+ Builder.defineMacro("__ARMEB__");
+ Builder.defineMacro("__ARM_BIG_ENDIAN");
+ }
ARMTargetInfo::getTargetDefines(Opts, Builder);
}
};
Index: lib/Headers/Intrin.h
===================================================================
--- lib/Headers/Intrin.h
+++ lib/Headers/Intrin.h
@@ -30,7 +30,7 @@
#define __INTRIN_H
/* First include the standard intrinsics. */
-#if defined(__i386__) || defined(__x86_64__)
+#if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) || defined(_M_X64)
#include <x86intrin.h>
#endif
Index: lib/Headers/ammintrin.h
===================================================================
--- lib/Headers/ammintrin.h
+++ lib/Headers/ammintrin.h
@@ -24,7 +24,7 @@
#ifndef __AMMINTRIN_H
#define __AMMINTRIN_H
-#ifndef __SSE4A__
+#if !defined(__SSE4A__) && !defined(_MSC_VER)
#error "SSE4A instruction set not enabled"
#else
Index: lib/Headers/arm_acle.h
===================================================================
--- lib/Headers/arm_acle.h
+++ lib/Headers/arm_acle.h
@@ -24,7 +24,7 @@
#ifndef __ARM_ACLE_H
#define __ARM_ACLE_H
-#ifndef __ARM_ACLE
+#if !defined(__ARM_ACLE) && !defined(_MSC_VER)
#error "ACLE intrinsics support not enabled."
#endif
Index: lib/Headers/emmintrin.h
===================================================================
--- lib/Headers/emmintrin.h
+++ lib/Headers/emmintrin.h
@@ -24,7 +24,7 @@
#ifndef __EMMINTRIN_H
#define __EMMINTRIN_H
-#ifndef __SSE2__
+#if !defined(__SSE2__) && !defined(_MSC_VER)
#error "SSE2 instruction set not enabled"
#else
Index: lib/Headers/fmaintrin.h
===================================================================
--- lib/Headers/fmaintrin.h
+++ lib/Headers/fmaintrin.h
@@ -28,7 +28,7 @@
#ifndef __FMAINTRIN_H
#define __FMAINTRIN_H
-#ifndef __FMA__
+#if !defined(__FMA__) && !defined(_MSC_VER)
# error "FMA instruction set is not enabled"
#else
Index: lib/Headers/immintrin.h
===================================================================
--- lib/Headers/immintrin.h
+++ lib/Headers/immintrin.h
@@ -24,39 +24,39 @@
#ifndef __IMMINTRIN_H
#define __IMMINTRIN_H
-#ifdef __MMX__
+#if defined(__MMX__) || defined(_MSC_VER)
#include <mmintrin.h>
#endif
-#ifdef __SSE__
+#if defined(__SSE__) || defined(_MSC_VER)
#include <xmmintrin.h>
#endif
-#ifdef __SSE2__
+#if defined(__SSE2__) || defined(_MSC_VER)
#include <emmintrin.h>
#endif
-#ifdef __SSE3__
+#if defined(__SSE3__) || defined(_MSC_VER)
#include <pmmintrin.h>
#endif
-#ifdef __SSSE3__
+#if defined(__SSSE3__) || defined(_MSC_VER)
#include <tmmintrin.h>
#endif
-#if defined (__SSE4_2__) || defined (__SSE4_1__)
+#if defined (__SSE4_2__) || defined (__SSE4_1__) || defined(_MSC_VER)
#include <smmintrin.h>
#endif
-#if defined (__AES__) || defined (__PCLMUL__)
+#if defined (__AES__) || defined (__PCLMUL__) || defined(_MSC_VER)
#include <wmmintrin.h>
#endif
-#ifdef __AVX__
+#if defined(__AVX__) || defined(_MSC_VER)
#include <avxintrin.h>
#endif
-#ifdef __AVX2__
+#if defined(__AVX2__) || defined(_MSC_VER)
#include <avx2intrin.h>
#endif
Index: lib/Headers/mmintrin.h
===================================================================
--- lib/Headers/mmintrin.h
+++ lib/Headers/mmintrin.h
@@ -24,7 +24,7 @@
#ifndef __MMINTRIN_H
#define __MMINTRIN_H
-#ifndef __MMX__
+#if !defined(__MMX__) && !defined(_MSC_VER)
#error "MMX instruction set not enabled"
#else
Index: lib/Headers/nmmintrin.h
===================================================================
--- lib/Headers/nmmintrin.h
+++ lib/Headers/nmmintrin.h
@@ -24,7 +24,7 @@
#ifndef _NMMINTRIN_H
#define _NMMINTRIN_H
-#ifndef __SSE4_2__
+#if !defined(__SSE_4_2__) && !defined(_MSC_VER)
#error "SSE4.2 instruction set not enabled"
#else
Index: lib/Headers/pmmintrin.h
===================================================================
--- lib/Headers/pmmintrin.h
+++ lib/Headers/pmmintrin.h
@@ -24,7 +24,7 @@
#ifndef __PMMINTRIN_H
#define __PMMINTRIN_H
-#ifndef __SSE3__
+#if !defined(__SSE3__) && !defined(_MSC_VER)
#error "SSE3 instruction set not enabled"
#else
Index: lib/Headers/smmintrin.h
===================================================================
--- lib/Headers/smmintrin.h
+++ lib/Headers/smmintrin.h
@@ -24,7 +24,7 @@
#ifndef _SMMINTRIN_H
#define _SMMINTRIN_H
-#ifndef __SSE4_1__
+#if !defined(__SSE4_1__) && !defined(_MSC_VER)
#error "SSE4.1 instruction set not enabled"
#else
Index: lib/Headers/tmmintrin.h
===================================================================
--- lib/Headers/tmmintrin.h
+++ lib/Headers/tmmintrin.h
@@ -24,7 +24,7 @@
#ifndef __TMMINTRIN_H
#define __TMMINTRIN_H
-#ifndef __SSSE3__
+#if !defined(__SSE3__) && !defined(_MSC_VER)
#error "SSSE3 instruction set not enabled"
#else
Index: lib/Headers/wmmintrin.h
===================================================================
--- lib/Headers/wmmintrin.h
+++ lib/Headers/wmmintrin.h
@@ -26,7 +26,7 @@
#include <emmintrin.h>
-#if !defined (__AES__) && !defined (__PCLMUL__)
+#if !defined (__AES__) && !defined (__PCLMUL__) && !defined (_MSC_VER)
# error "AES/PCLMUL instructions not enabled"
#else
Index: lib/Headers/x86intrin.h
===================================================================
--- lib/Headers/x86intrin.h
+++ lib/Headers/x86intrin.h
@@ -28,7 +28,7 @@
#include <immintrin.h>
-#ifdef __3dNOW__
+#if defined(__3dNOW__) || defined(_MSC_VER)
#include <mm3dnow.h>
#endif
@@ -56,7 +56,7 @@
#include <prfchwintrin.h>
#endif
-#ifdef __SSE4A__
+#if defined(_SSE4A__) || defined(_MSC_VER)
#include <ammintrin.h>
#endif
Index: lib/Headers/xmmintrin.h
===================================================================
--- lib/Headers/xmmintrin.h
+++ lib/Headers/xmmintrin.h
@@ -24,7 +24,7 @@
#ifndef __XMMINTRIN_H
#define __XMMINTRIN_H
-#ifndef __SSE__
+#if !defined(__SSE__) && !defined(_MSC_VER)
#error "SSE instruction set not enabled"
#else
Index: test/CodeGenCXX/mangle-ms-vector-types.cpp
===================================================================
--- test/CodeGenCXX/mangle-ms-vector-types.cpp
+++ test/CodeGenCXX/mangle-ms-vector-types.cpp
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -fms-extensions -ffreestanding -target-feature +avx -emit-llvm %s -o - -triple=i686-pc-win32 | FileCheck %s
+// RUN: %clang_cc1 -fms-extensions -fmsc-version=1700 -ffreestanding -target-feature +avx -emit-llvm %s -o - -triple=i686-pc-win32 | FileCheck %s
#include <xmmintrin.h>
#include <emmintrin.h>
Index: test/Preprocessor/predefined-macros.c
===================================================================
--- test/Preprocessor/predefined-macros.c
+++ test/Preprocessor/predefined-macros.c
@@ -10,6 +10,27 @@
// CHECK-MS: #define _WIN32 1
// CHECK-MS-NOT: #define __GNUC__
// CHECK-MS-NOT: #define __STRICT_ANSI__
+// CHECK-MS-NOT: #define __i386__
+// CHECK-MS-NOT: #define __i486__
+// CHECK-MS-NOT: #define __i686__
+// CHECK-MS-NOT: #define __SSE__
+//
+// RUN: %clang_cc1 %s -E -dM -triple x86_64-pc-win32 -fms-extensions -fms-compatibility \
+// RUN: -fmsc-version=1300 -o - | FileCheck %s --check-prefix=CHECK-MS64
+// CHECK-MS64: #define _INTEGRAL_MAX_BITS 64
+// CHECK-MS64: #define _MSC_EXTENSIONS 1
+// CHECK-MS64: #define _MSC_VER 1300
+// CHECK-MS64: #define _M_AMD64 1
+// CHECK-MS64: #define _M_X64 1
+// CHECK-MS64: #define _WIN64 1
+// CHECK-MS64-NOT: #define __GNUC__
+// CHECK-MS64-NOT: #define __STRICT_ANSI__
+// CHECK-MS64-NOT: #define __i486__
+// CHECK-MS64-NOT: #define __i686__
+// CHECK-MS64-NOT: #define __i386__
+// CHECK-MS64-NOT: #define __SSE__
+// CHECK-MS64-NOT: #define __x86_64__
+// CHECK-MS64-NOT: #define __amd64__
//
// RUN: %clang_cc1 %s -E -dM -triple i686-pc-win32 -fms-compatibility \
// RUN: -o - | FileCheck %s --check-prefix=CHECK-MS-STDINT
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