Hi,
This patch adds the following predefined macros:
__ARM_FEATURE_DIRECTED_ROUNDING
__ARM_FEATURE_NUMERIC_MAXMIN
__ARM_FEATURE_IDIV
Note that these are related to Graham Hunter¹s patch, (AArch32 v8 NEON
intrinsics for numeric max/min and directed rounding to integral), and were
unit tested together.
-Assad
diff --git include/clang/Basic/arm_neon.td include/clang/Basic/arm_neon.td
index 0247bb5..ce3b609 100644
--- include/clang/Basic/arm_neon.td
+++ include/clang/Basic/arm_neon.td
@@ -944,13 +944,6 @@ def VCVT_F64 : SInst<"vcvt_f64", "Fd", "lUlQlQUl">;
def VCVT_HIGH_F64_F32 : SOpInst<"vcvt_high_f64", "wj", "f", OP_VCVT_EX_HI_F64>;
def VCVTX_F32_F64 : SInst<"vcvtx_f32", "fj", "d">;
def VCVTX_HIGH_F32_F64 : SOpInst<"vcvtx_high_f32", "qfj", "d", OP_VCVTX_HI>;
-def FRINTN : SInst<"vrndn", "dd", "fdQfQd">;
-def FRINTA : SInst<"vrnda", "dd", "fdQfQd">;
-def FRINTP : SInst<"vrndp", "dd", "fdQfQd">;
-def FRINTM : SInst<"vrndm", "dd", "fdQfQd">;
-def FRINTX : SInst<"vrndx", "dd", "fdQfQd">;
-def FRINTZ : SInst<"vrnd", "dd", "fdQfQd">;
-def FRINTI : SInst<"vrndi", "dd", "fdQfQd">;
def VCVT_S64 : SInst<"vcvt_s64", "xd", "dQd">;
def VCVT_U64 : SInst<"vcvt_u64", "ud", "dQd">;
def FRECPE : SInst<"vrecpe", "dd", "dQd">;
@@ -983,11 +976,6 @@ def MAX : SInst<"vmax", "ddd", "dQd">;
def MIN : SInst<"vmin", "ddd", "dQd">;
////////////////////////////////////////////////////////////////////////////////
-// MaxNum/MinNum Floating Point
-def FMAXNM : SInst<"vmaxnm", "ddd", "fdQfQd">;
-def FMINNM : SInst<"vminnm", "ddd", "fdQfQd">;
-
-////////////////////////////////////////////////////////////////////////////////
// Pairwise Max/Min
def MAXP : SInst<"vpmax", "ddd", "QcQsQiQUcQUsQUiQfQd">;
def MINP : SInst<"vpmin", "ddd", "QcQsQiQUcQUsQUiQfQd">;
@@ -1223,6 +1211,41 @@ def FCVTAU_S64 : SInst<"vcvta_u64", "ud", "dQd">;
}
////////////////////////////////////////////////////////////////////////////////
+// Round to Integral
+
+let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_DIRECTED_ROUNDING)"
in {
+def FRINTN_S32 : SInst<"vrndn", "dd", "fQf">;
+def FRINTA_S32 : SInst<"vrnda", "dd", "fQf">;
+def FRINTP_S32 : SInst<"vrndp", "dd", "fQf">;
+def FRINTM_S32 : SInst<"vrndm", "dd", "fQf">;
+def FRINTX_S32 : SInst<"vrndx", "dd", "fQf">;
+def FRINTZ_S32 : SInst<"vrnd", "dd", "fQf">;
+}
+
+let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__) &&
defined(__ARM_FEATURE_DIRECTED_ROUNDING)" in {
+def FRINTN_S64 : SInst<"vrndn", "dd", "dQd">;
+def FRINTA_S64 : SInst<"vrnda", "dd", "dQd">;
+def FRINTP_S64 : SInst<"vrndp", "dd", "dQd">;
+def FRINTM_S64 : SInst<"vrndm", "dd", "dQd">;
+def FRINTX_S64 : SInst<"vrndx", "dd", "dQd">;
+def FRINTZ_S64 : SInst<"vrnd", "dd", "dQd">;
+def FRINTI_S64 : SInst<"vrndi", "dd", "fdQfQd">;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// MaxNum/MinNum Floating Point
+
+let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_NUMERIC_MAXMIN)" in {
+def FMAXNM_S32 : SInst<"vmaxnm", "ddd", "fQf">;
+def FMINNM_S32 : SInst<"vminnm", "ddd", "fQf">;
+}
+
+let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__) &&
defined(__ARM_FEATURE_NUMERIC_MAXMIN)" in {
+def FMAXNM_S64 : SInst<"vmaxnm", "ddd", "dQd">;
+def FMINNM_S64 : SInst<"vminnm", "ddd", "dQd">;
+}
+
+////////////////////////////////////////////////////////////////////////////////
// Permutation
def VTRN1 : SOpInst<"vtrn1", "ddd",
"csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl",
OP_TRN1>;
diff --git lib/Basic/Targets.cpp lib/Basic/Targets.cpp
index 4998ca3..60f194c 100644
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -3983,6 +3983,10 @@ public:
// __ARM_ARCH is defined as an integer value indicating the current ARM ISA
Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
+ if (CPUArch[0] >= '8') {
+ Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
+ Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
+ }
// __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It
// is not defined for the M-profile.
@@ -4477,7 +4481,10 @@ public:
Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
Builder.defineMacro("__ARM_FEATURE_CLZ");
Builder.defineMacro("__ARM_FEATURE_FMA");
- Builder.defineMacro("__ARM_FEATURE_DIV");
+ Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE
+ Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility
+ Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
+ Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
diff --git lib/CodeGen/CGBuiltin.cpp lib/CodeGen/CGBuiltin.cpp
index b74038e..7decbbd 100644
--- lib/CodeGen/CGBuiltin.cpp
+++ lib/CodeGen/CGBuiltin.cpp
@@ -2009,8 +2009,12 @@ static NeonIntrinsicInfo ARMSIMDIntrinsicMap [] = {
NEONMAP1(vld4q_lane_v, arm_neon_vld4lane, 0),
NEONMAP1(vld4q_v, arm_neon_vld4, 0),
NEONMAP2(vmax_v, arm_neon_vmaxu, arm_neon_vmaxs, Add1ArgType | UnsignedAlts),
+ NEONMAP1(vmaxnm_v, arm_neon_vmaxnm, Add1ArgType),
+ NEONMAP1(vmaxnmq_v, arm_neon_vmaxnm, Add1ArgType),
NEONMAP2(vmaxq_v, arm_neon_vmaxu, arm_neon_vmaxs, Add1ArgType |
UnsignedAlts),
NEONMAP2(vmin_v, arm_neon_vminu, arm_neon_vmins, Add1ArgType | UnsignedAlts),
+ NEONMAP1(vminnm_v, arm_neon_vminnm, Add1ArgType),
+ NEONMAP1(vminnmq_v, arm_neon_vminnm, Add1ArgType),
NEONMAP2(vminq_v, arm_neon_vminu, arm_neon_vmins, Add1ArgType |
UnsignedAlts),
NEONMAP0(vmovl_v),
NEONMAP0(vmovn_v),
@@ -2057,6 +2061,18 @@ static NeonIntrinsicInfo ARMSIMDIntrinsicMap [] = {
NEONMAP1(vrecpsq_v, arm_neon_vrecps, Add1ArgType),
NEONMAP2(vrhadd_v, arm_neon_vrhaddu, arm_neon_vrhadds, Add1ArgType |
UnsignedAlts),
NEONMAP2(vrhaddq_v, arm_neon_vrhaddu, arm_neon_vrhadds, Add1ArgType |
UnsignedAlts),
+ NEONMAP1(vrnd_v, arm_neon_vrintz, Add1ArgType),
+ NEONMAP1(vrnda_v, arm_neon_vrinta, Add1ArgType),
+ NEONMAP1(vrndaq_v, arm_neon_vrinta, Add1ArgType),
+ NEONMAP1(vrndm_v, arm_neon_vrintm, Add1ArgType),
+ NEONMAP1(vrndmq_v, arm_neon_vrintm, Add1ArgType),
+ NEONMAP1(vrndn_v, arm_neon_vrintn, Add1ArgType),
+ NEONMAP1(vrndnq_v, arm_neon_vrintn, Add1ArgType),
+ NEONMAP1(vrndp_v, arm_neon_vrintp, Add1ArgType),
+ NEONMAP1(vrndpq_v, arm_neon_vrintp, Add1ArgType),
+ NEONMAP1(vrndq_v, arm_neon_vrintz, Add1ArgType),
+ NEONMAP1(vrndx_v, arm_neon_vrintx, Add1ArgType),
+ NEONMAP1(vrndxq_v, arm_neon_vrintx, Add1ArgType),
NEONMAP2(vrshl_v, arm_neon_vrshiftu, arm_neon_vrshifts, Add1ArgType |
UnsignedAlts),
NEONMAP2(vrshlq_v, arm_neon_vrshiftu, arm_neon_vrshifts, Add1ArgType |
UnsignedAlts),
NEONMAP2(vrshr_n_v, arm_neon_vrshiftu, arm_neon_vrshifts, UnsignedAlts),
diff --git test/Preprocessor/aarch64-target-features.c
test/Preprocessor/aarch64-target-features.c
index 137a1d8..74764c2 100644
--- test/Preprocessor/aarch64-target-features.c
+++ test/Preprocessor/aarch64-target-features.c
@@ -12,8 +12,11 @@
// CHECK: __ARM_FEATURE_CLZ 1
// CHECK-NOT: __ARM_FEATURE_CRC32 1
// CHECK-NOT: __ARM_FEATURE_CRYPTO 1
+// CHECK: __ARM_FEATURE_DIRECTED_ROUNDING 1
// CHECK: __ARM_FEATURE_DIV 1
// CHECK: __ARM_FEATURE_FMA 1
+// CHECK: __ARM_FEATURE_IDIV 1
+// CHECK: __ARM_FEATURE_NUMERIC_MAXMIN 1
// CHECK: __ARM_FEATURE_UNALIGNED 1
// CHECK: __ARM_FP 0xe
// CHECK: __ARM_FP16_FORMAT_IEEE 1
diff --git test/Preprocessor/arm-acle-6.4.c test/Preprocessor/arm-acle-6.4.c
index a656f76..fc228d0 100644
--- test/Preprocessor/arm-acle-6.4.c
+++ test/Preprocessor/arm-acle-6.4.c
@@ -5,6 +5,8 @@
// CHECK-CORTEX-M0-NOT: __ARM_ARCH_ISA_ARM
// CHECK-CORTEX-M0: __ARM_ARCH_ISA_THUMB 1
// CHECK-CORTEX-M0: __ARM_ARCH_PROFILE 'M'
+// CHECK-CORTEX-M0-NOT: __ARM_FEATURE_NUMERIC_MAXMIN
+// CHECK-CORTEX-M0-NOT: __ARM_FEATURE_DIRECTED_ROUNDING
// RUN: %clang -target arm-eabi -mcpu=arm810 -x c -E -dM %s -o - | FileCheck
%s -check-prefix CHECK-ARM810
@@ -13,6 +15,8 @@
// CHECK-ARM810: __ARM_ARCH_ISA_ARM 1
// CHECK-ARM810-NOT: __ARM_ARCH_ISA_THUMB
// CHECK-ARM810-NOT: __ARM_ARCH_PROFILE
+// CHECK-ARM810-NOT: __ARM_FEATURE_NUMERIC_MAXMIN
+// CHECK-ARM810-NOT: __ARM_FEATURE_DIRECTED_ROUNDING
// RUN: %clang -target arm-eabi -mcpu=arm7tdmi -x c -E -dM %s -o - | FileCheck
%s -check-prefix CHECK-ARM7TDMI
@@ -29,6 +33,8 @@
// CHECK-CORTEX-A7: __ARM_ARCH_ISA_ARM 1
// CHECK-CORTEX-A7: __ARM_ARCH_ISA_THUMB 2
// CHECK-CORTEX-A7: __ARM_ARCH_PROFILE 'A'
+// CHECK-CORTEX-A7-NOT: __ARM_FEATURE_NUMERIC_MAXMIN
+// CHECK-CORTEX-A7-NOT: __ARM_FEATURE_DIRECTED_ROUNDING
// RUN: %clang -target arm-eabi -mcpu=cortex-r4 -x c -E -dM %s -o - |
FileCheck %s -check-prefix CHECK-CORTEX-R4
diff --git test/Preprocessor/arm-target-features.c
test/Preprocessor/arm-target-features.c
index 08fe29a..4759039 100644
--- test/Preprocessor/arm-target-features.c
+++ test/Preprocessor/arm-target-features.c
@@ -3,18 +3,24 @@
// CHECK: __ARM_ARCH 8
// CHECK: __ARM_ARCH_8A__ 1
// CHECK: __ARM_FEATURE_CRC32 1
+// CHECK: __ARM_FEATURE_DIRECTED_ROUNDING 1
+// CHECK: __ARM_FEATURE_NUMERIC_MAXMIN 1
// RUN: %clang -target armv7a-none-linux-gnu -x c -E -dM %s -o - | FileCheck
--check-prefix=CHECK-V7 %s
// CHECK-V7: __ARMEL__ 1
// CHECK-V7: __ARM_ARCH 7
// CHECK-V7: __ARM_ARCH_7A__ 1
// CHECK-V7-NOT: __ARM_FEATURE_CRC32
+// CHECK-V7-NOT: __ARM_FEATURE_NUMERIC_MAXMIN
+// CHECK-V7-NOT: __ARM_FEATURE_DIRECTED_ROUNDING
// RUN: %clang -target armv8a -mfloat-abi=hard -x c -E -dM %s | FileCheck
--check-prefix=CHECK-V8-BAREHF %s
// CHECK-V8-BAREHF: __ARMEL__ 1
// CHECK-V8-BAREHF: __ARM_ARCH 8
// CHECK-V8-BAREHF: __ARM_ARCH_8A__ 1
// CHECK-V8-BAREHF: __ARM_FEATURE_CRC32 1
+// CHECK-V8-BAREHF: __ARM_FEATURE_DIRECTED_ROUNDING 1
+// CHECK-V8-BAREHF: __ARM_FEATURE_NUMERIC_MAXMIN 1
// CHECK-V8-BAREHF: __ARM_NEON__ 1
// CHECK-V8-BAREHF: __VFP_FP__ 1
@@ -149,6 +155,8 @@
// A5:#define __ARM_ARCH 7
// A5:#define __ARM_ARCH_7A__ 1
// A5:#define __ARM_ARCH_PROFILE 'A'
+// A5-NOT: #define __ARM_FEATURE_NUMERIC_MAXMIN
+// A5-NOT: #define __ARM_FEATURE_DIRECTED_ROUNDING
// Test whether predefines are as expected when targeting cortex-a7.
// RUN: %clang -target armv7 -mcpu=cortex-a7 -x c -E -dM %s -o - | FileCheck
--check-prefix=A7 %s
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