https://github.com/mshockwave updated
https://github.com/llvm/llvm-project/pull/137725
>From c8584c12408bcf8739558b3d9e0c2190f1d95bea Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min....@sifive.com>
Date: Mon, 28 Apr 2025 14:12:13 -0700
Subject: [PATCH 1/2] [RISCV] Add processor definition for SiFive P870
---
.../riscv-sifive-p870.c | 81 +++++++++++++++++++
clang/test/Driver/riscv-cpus.c | 5 ++
.../test/Misc/target-invalid-cpu-note/riscv.c | 2 +
llvm/docs/ReleaseNotes.md | 1 +
llvm/lib/Target/RISCV/RISCVProcessors.td | 26 ++++++
5 files changed, 115 insertions(+)
create mode 100644
clang/test/Driver/print-enabled-extensions/riscv-sifive-p870.c
diff --git a/clang/test/Driver/print-enabled-extensions/riscv-sifive-p870.c
b/clang/test/Driver/print-enabled-extensions/riscv-sifive-p870.c
new file mode 100644
index 0000000000000..f76e5daec672b
--- /dev/null
+++ b/clang/test/Driver/print-enabled-extensions/riscv-sifive-p870.c
@@ -0,0 +1,81 @@
+// RUN: %clang --target=riscv64 -mcpu=sifive-p870 --print-enabled-extensions |
FileCheck %s
+// REQUIRES: riscv-registered-target
+
+// CHECK: Extensions enabled for the given RISC-V target
+// CHECK-EMPTY:
+// CHECK-NEXT: Name Version Description
+// CHECK-NEXT: i 2.1 'I' (Base Integer
Instruction Set)
+// CHECK-NEXT: m 2.0 'M' (Integer Multiplication
and Division)
+// CHECK-NEXT: a 2.1 'A' (Atomic Instructions)
+// CHECK-NEXT: f 2.2 'F' (Single-Precision
Floating-Point)
+// CHECK-NEXT: d 2.2 'D' (Double-Precision
Floating-Point)
+// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
+// CHECK-NEXT: b 1.0 'B' (the collection of the
Zba, Zbb, Zbs extensions)
+// CHECK-NEXT: v 1.0 'V' (Vector Extension for
Application Processors)
+// CHECK-NEXT: zic64b 1.0 'Zic64b' (Cache Block Size
Is 64 Bytes)
+// CHECK-NEXT: zicbom 1.0 'Zicbom' (Cache-Block
Management Instructions)
+// CHECK-NEXT: zicbop 1.0 'Zicbop' (Cache-Block
Prefetch Instructions)
+// CHECK-NEXT: zicboz 1.0 'Zicboz' (Cache-Block Zero
Instructions)
+// CHECK-NEXT: ziccamoa 1.0 'Ziccamoa' (Main Memory
Supports All Atomics in A)
+// CHECK-NEXT: ziccif 1.0 'Ziccif' (Main Memory
Supports Instruction Fetch with Atomicity Requirement)
+// CHECK-NEXT: zicclsm 1.0 'Zicclsm' (Main Memory
Supports Misaligned Loads/Stores)
+// CHECK-NEXT: ziccrse 1.0 'Ziccrse' (Main Memory
Supports Forward Progress on LR/SC Sequences)
+// CHECK-NEXT: zicntr 2.0 'Zicntr' (Base Counters and
Timers)
+// CHECK-NEXT: zicond 1.0 'Zicond' (Integer
Conditional Operations)
+// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
+// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
+// CHECK-NEXT: zihintntl 1.0 'Zihintntl' (Non-Temporal
Locality Hints)
+// CHECK-NEXT: zihintpause 2.0 'Zihintpause' (Pause Hint)
+// CHECK-NEXT: zihpm 2.0 'Zihpm' (Hardware
Performance Counters)
+// CHECK-NEXT: zimop 1.0 'Zimop' (May-Be-Operations)
+// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer
Multiplication)
+// CHECK-NEXT: za64rs 1.0 'Za64rs' (Reservation Set
Size of at Most 64 Bytes)
+// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory
Operations)
+// CHECK-NEXT: zalrsc 1.0 'Zalrsc'
(Load-Reserved/Store-Conditional)
+// CHECK-NEXT: zama16b 1.0 'Zama16b' (Atomic 16-byte
misaligned loads, stores and AMOs)
+// CHECK-NEXT: zawrs 1.0 'Zawrs' (Wait on Reservation
Set)
+// CHECK-NEXT: zfa 1.0 'Zfa' (Additional
Floating-Point)
+// CHECK-NEXT: zfbfmin 1.0 'Zfbfmin' (Scalar BF16
Converts)
+// CHECK-NEXT: zfh 1.0 'Zfh' (Half-Precision
Floating-Point)
+// CHECK-NEXT: zfhmin 1.0 'Zfhmin' (Half-Precision
Floating-Point Minimal)
+// CHECK-NEXT: zca 1.0 'Zca' (part of the C
extension, excluding compressed floating point loads/stores)
+// CHECK-NEXT: zcb 1.0 'Zcb' (Compressed basic bit
manipulation instructions)
+// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed
Double-Precision Floating-Point Instructions)
+// CHECK-NEXT: zcmop 1.0 'Zcmop' (Compressed
May-Be-Operations)
+// CHECK-NEXT: zba 1.0 'Zba' (Address Generation
Instructions)
+// CHECK-NEXT: zbb 1.0 'Zbb' (Basic
Bit-Manipulation)
+// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit
Instructions)
+// CHECK-NEXT: zkr 1.0 'Zkr' (Entropy Source
Extension)
+// CHECK-NEXT: zkt 1.0 'Zkt' (Data Independent
Execution Latency)
+// CHECK-NEXT: zvbb 1.0 'Zvbb' (Vector basic
bit-manipulation instructions)
+// CHECK-NEXT: zvbc 1.0 'Zvbc' (Vector Carryless
Multiplication)
+// CHECK-NEXT: zve32f 1.0 'Zve32f' (Vector Extensions
for Embedded Processors with maximal 32 EEW and F extension)
+// CHECK-NEXT: zve32x 1.0 'Zve32x' (Vector Extensions
for Embedded Processors with maximal 32 EEW)
+// CHECK-NEXT: zve64d 1.0 'Zve64d' (Vector Extensions
for Embedded Processors with maximal 64 EEW, F and D extension)
+// CHECK-NEXT: zve64f 1.0 'Zve64f' (Vector Extensions
for Embedded Processors with maximal 64 EEW and F extension)
+// CHECK-NEXT: zve64x 1.0 'Zve64x' (Vector Extensions
for Embedded Processors with maximal 64 EEW)
+// CHECK-NEXT: zvfbfmin 1.0 'Zvfbfmin' (Vector BF16
Converts)
+// CHECK-NEXT: zvfbfwma 1.0 'Zvfbfwma' (Vector BF16
widening mul-add)
+// CHECK-NEXT: zvfh 1.0 'Zvfh' (Vector
Half-Precision Floating-Point)
+// CHECK-NEXT: zvfhmin 1.0 'Zvfhmin' (Vector
Half-Precision Floating-Point Minimal)
+// CHECK-NEXT: zvkb 1.0 'Zvkb' (Vector
Bit-manipulation used in Cryptography)
+// CHECK-NEXT: zvkg 1.0 'Zvkg' (Vector GCM
instructions for Cryptography)
+// CHECK-NEXT: zvkn 1.0 'Zvkn' (shorthand for
'Zvkned', 'Zvknhb', 'Zvkb', and 'Zvkt')
+// CHECK-NEXT: zvknc 1.0 'Zvknc' (shorthand for
'Zvknc' and 'Zvbc')
+// CHECK-NEXT: zvkned 1.0 'Zvkned' (Vector AES
Encryption & Decryption (Single Round))
+// CHECK-NEXT: zvkng 1.0 'Zvkng' (shorthand for
'Zvkn' and 'Zvkg')
+// CHECK-NEXT: zvknhb 1.0 'Zvknhb' (Vector SHA-2
(SHA-256 and SHA-512))
+// CHECK-NEXT: zvks 1.0 'Zvks' (shorthand for
'Zvksed', 'Zvksh', 'Zvkb', and 'Zvkt')
+// CHECK-NEXT: zvksc 1.0 'Zvksc' (shorthand for
'Zvks' and 'Zvbc')
+// CHECK-NEXT: zvksed 1.0 'Zvksed' (SM4 Block Cipher
Instructions)
+// CHECK-NEXT: zvksg 1.0 'Zvksg' (shorthand for
'Zvks' and 'Zvkg')
+// CHECK-NEXT: zvksh 1.0 'Zvksh' (SM3 Hash Function
Instructions)
+// CHECK-NEXT: zvkt 1.0 'Zvkt' (Vector
Data-Independent Execution Latency)
+// CHECK-NEXT: zvl128b 1.0 'Zvl128b' (Minimum Vector
Length 128)
+// CHECK-NEXT: zvl32b 1.0 'Zvl32b' (Minimum Vector
Length 32)
+// CHECK-NEXT: zvl64b 1.0 'Zvl64b' (Minimum Vector
Length 64)
+// CHECK-NEXT: supm 1.0 'Supm' (Indicates User-mode
Pointer Masking)
+// CHECK-EMPTY:
+// CHECK-NEXT: Experimental extensions
+// CHECK-EMPTY:
+// CHECK-NEXT: ISA String:
rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zama16b1p0_zawrs1p0_zfa1p0_zfbfmin1p0_zfh1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkr1p0_zkt1p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvfbfwma1p0_zvfh1p0_zvfhmin1p0_zvkb1p0_zvkg1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvkng1p0_zvknhb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_supm1p0
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index bb3a9d38be673..cf939bd85358d 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -566,6 +566,11 @@
// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkt"
// MCPU-SIFIVE-P670-SAME: "-target-abi" "lp64d"
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p870 | FileCheck
-check-prefix=MCPU-SIFIVE-P870 %s
+// MCPU-SIFIVE-P870: "-target-cpu" "sifive-p870"
+// COM: The list of extensions are tested in
`test/Driver/print-enabled-extensions/riscv-sifive-p870.c`
+// MCPU-SIFIVE-P870-SAME: "-target-abi" "lp64d"
+
// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=rp2350-hazard3 |
FileCheck -check-prefix=MCPU-HAZARD3 %s
// MCPU-HAZARD3: "-target-cpu" "rp2350-hazard3"
// MCPU-HAZARD3-SAME: "-target-feature" "+m"
diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c
b/clang/test/Misc/target-invalid-cpu-note/riscv.c
index f0c4173e18022..b4e83e59d296f 100644
--- a/clang/test/Misc/target-invalid-cpu-note/riscv.c
+++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c
@@ -35,6 +35,7 @@
// RISCV64-SAME: {{^}}, sifive-p470
// RISCV64-SAME: {{^}}, sifive-p550
// RISCV64-SAME: {{^}}, sifive-p670
+// RISCV64-SAME: {{^}}, sifive-p870
// RISCV64-SAME: {{^}}, sifive-s21
// RISCV64-SAME: {{^}}, sifive-s51
// RISCV64-SAME: {{^}}, sifive-s54
@@ -90,6 +91,7 @@
// TUNE-RISCV64-SAME: {{^}}, sifive-p470
// TUNE-RISCV64-SAME: {{^}}, sifive-p550
// TUNE-RISCV64-SAME: {{^}}, sifive-p670
+// TUNE-RISCV64-SAME: {{^}}, sifive-p870
// TUNE-RISCV64-SAME: {{^}}, sifive-s21
// TUNE-RISCV64-SAME: {{^}}, sifive-s51
// TUNE-RISCV64-SAME: {{^}}, sifive-s54
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 9e2e63cffdf82..fe65046cf1c15 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -176,6 +176,7 @@ Changes to the RISC-V Backend
* Adds Support for SiFive CLIC interrupt attributes, which automate writing
CLIC
interrupt handlers without using inline assembly.
* Adds assembler support for the Andes `XAndesperf` (Andes Performance
extension).
+* `-mcpu=sifive-p870` was added.
Changes to the WebAssembly Backend
----------------------------------
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 1ad94228bcbaa..5425a1399a359 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -365,6 +365,32 @@ def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670",
SiFiveP600Model,
TuneVXRMPipelineFlush,
TunePostRAScheduler]>;
+def SIFIVE_P870 : RISCVProcessorModel<"sifive-p870", NoSchedModel,
+ !listconcat(RVA23U64Features,
+ [FeatureStdExtZama16b,
+ FeatureStdExtZfh,
+ FeatureStdExtZifencei,
+ FeatureStdExtZihintntl,
+ FeatureStdExtZkr,
+ FeatureStdExtZvbb,
+ FeatureStdExtZvfbfmin,
+ FeatureStdExtZvfbfwma,
+ FeatureStdExtZvfh,
+ FeatureStdExtZvknc,
+ FeatureStdExtZvkng,
+ FeatureStdExtZvksc,
+ FeatureStdExtZvksg,
+ FeatureStdExtZvl128b,
+ FeatureUnalignedScalarMem,
+ FeatureUnalignedVectorMem]),
+ [TuneNoDefaultUnroll,
+ TuneConditionalCompressedMoveFusion,
+ TuneLUIADDIFusion,
+ TuneAUIPCADDIFusion,
+ TuneNoSinkSplatOperands,
+ TuneVXRMPipelineFlush,
+ TunePostRAScheduler]>;
+
def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
SyntacoreSCR1Model,
[Feature32Bit,
>From 2b1fa14f32a5522ef93dbd4dbedf5ce744fccede Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min....@sifive.com>
Date: Tue, 29 Apr 2025 10:45:41 -0700
Subject: [PATCH 2/2] fixup! Remove redundant extensions
---
llvm/lib/Target/RISCV/RISCVProcessors.td | 2 --
1 file changed, 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 5425a1399a359..30c8bfb88544b 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -370,9 +370,7 @@ def SIFIVE_P870 : RISCVProcessorModel<"sifive-p870",
NoSchedModel,
[FeatureStdExtZama16b,
FeatureStdExtZfh,
FeatureStdExtZifencei,
- FeatureStdExtZihintntl,
FeatureStdExtZkr,
- FeatureStdExtZvbb,
FeatureStdExtZvfbfmin,
FeatureStdExtZvfbfwma,
FeatureStdExtZvfh,
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