[clang] [llvm] [RISCV] Add processor definition for SiFive P870 (PR #137725)

[Craig Topper via cfe-commits]

================
@@ -365,6 +365,32 @@ def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", 
SiFiveP600Model,
                                        TuneVXRMPipelineFlush,
                                        TunePostRAScheduler]>;
 
+def SIFIVE_P870 : RISCVProcessorModel<"sifive-p870", NoSchedModel,
+                                      !listconcat(RVA23U64Features,
+                                      [FeatureStdExtZama16b,
+                                       FeatureStdExtZfh,
+                                       FeatureStdExtZifencei,
+                                       FeatureStdExtZihintntl,
+                                       FeatureStdExtZkr,
+                                       FeatureStdExtZvbb,
+                                       FeatureStdExtZvfbfmin,
+                                       FeatureStdExtZvfbfwma,
+                                       FeatureStdExtZvfh,
+                                       FeatureStdExtZvknc,
+                                       FeatureStdExtZvkng,
+                                       FeatureStdExtZvksc,
+                                       FeatureStdExtZvksg,
+                                       FeatureStdExtZvl128b,
+                                       FeatureUnalignedScalarMem,
+                                       FeatureUnalignedVectorMem]),
+                                      [TuneNoDefaultUnroll,
+                                       TuneConditionalCompressedMoveFusion,
+                                       TuneLUIADDIFusion,
+                                       TuneAUIPCADDIFusion,
+                                       TuneNoSinkSplatOperands,
+                                       TuneVXRMPipelineFlush,
----------------
topperc wrote:

Where did you get that impression?

https://github.com/llvm/llvm-project/pull/137725
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