================ @@ -365,6 +365,32 @@ def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model, TuneVXRMPipelineFlush, TunePostRAScheduler]>; +def SIFIVE_P870 : RISCVProcessorModel<"sifive-p870", NoSchedModel, + !listconcat(RVA23U64Features, + [FeatureStdExtZama16b, + FeatureStdExtZfh, + FeatureStdExtZifencei, + FeatureStdExtZihintntl, + FeatureStdExtZkr, + FeatureStdExtZvbb, + FeatureStdExtZvfbfmin, + FeatureStdExtZvfbfwma, + FeatureStdExtZvfh, + FeatureStdExtZvknc, + FeatureStdExtZvkng, + FeatureStdExtZvksc, + FeatureStdExtZvksg, + FeatureStdExtZvl128b, + FeatureUnalignedScalarMem, + FeatureUnalignedVectorMem]), + [TuneNoDefaultUnroll, + TuneConditionalCompressedMoveFusion, + TuneLUIADDIFusion, + TuneAUIPCADDIFusion, + TuneNoSinkSplatOperands, ---------------- topperc wrote:
Where did you get that impression? https://github.com/llvm/llvm-project/pull/137725 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits