https://github.com/woruyu updated https://github.com/llvm/llvm-project/pull/169464
>From 1039154cd4b2d638a918946b22b88c5439d74ebd Mon Sep 17 00:00:00 2001 From: woruyu <[email protected]> Date: Tue, 3 Feb 2026 15:13:55 +0800 Subject: [PATCH] [CIR] Add X86 vector masked load builtins --- clang/lib/CIR/CodeGen/CIRGenBuilder.h | 17 +++++++++++++++++ clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp | 18 ++++++++++++++++++ .../CodeGenBuiltins/X86/avx512vl-builtins.c | 14 ++++++++++++++ 3 files changed, 49 insertions(+) diff --git a/clang/lib/CIR/CodeGen/CIRGenBuilder.h b/clang/lib/CIR/CodeGen/CIRGenBuilder.h index dedb369bf3f67..af076a571de5c 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuilder.h +++ b/clang/lib/CIR/CodeGen/CIRGenBuilder.h @@ -654,6 +654,23 @@ class CIRGenBuilderTy : public cir::CIRBaseBuilderTy { addr.getAlignment().getAsAlign().value()); } + mlir::Value createMaskedLoad(mlir::Location loc, mlir::Type ty, + mlir::Value ptr, mlir::Value mask, + mlir::Value passThru) { + + assert(mlir::isa<cir::VectorType>(ty) && "Type should be vector"); + assert(mask && "Mask should not be all-ones (null)"); + + if (!passThru) + passThru = this->getConstant(loc, cir::PoisonAttr::get(ty)); + + mlir::Value ops[] = {ptr, mask, passThru}; + + return cir::LLVMIntrinsicCallOp::create( + *this, loc, getStringAttr("masked.load"), ty, ops) + .getResult(); + } + cir::VecShuffleOp createVecShuffle(mlir::Location loc, mlir::Value vec1, mlir::Value vec2, llvm::ArrayRef<mlir::Attribute> maskAttrs) { diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp index 80022998448ad..3bec4cb5f4417 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp @@ -759,6 +759,17 @@ static mlir::Value emitX86Aeswide(CIRGenBuilderTy &builder, mlir::Location loc, return cir::ExtractMemberOp::create(builder, loc, rstValueRec, /*index=*/0); } +static mlir::Value emitX86MaskedLoad(CIRGenBuilderTy &builder, + ArrayRef<mlir::Value> ops, + mlir::Location loc) { + mlir::Type ty = ops[1].getType(); + mlir::Value ptr = ops[0]; + mlir::Value maskVec = getMaskVecValue(builder, loc, ops[2], + cast<cir::VectorType>(ty).getSize()); + + return builder.createMaskedLoad(loc, ty, ptr, maskVec, ops[1]); +} + std::optional<mlir::Value> CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, const CallExpr *expr) { if (builtinID == Builtin::BI__builtin_cpu_is) { @@ -1112,6 +1123,11 @@ CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, const CallExpr *expr) { case X86::BI__builtin_ia32_movdqa64store512_mask: case X86::BI__builtin_ia32_storeaps512_mask: case X86::BI__builtin_ia32_storeapd512_mask: + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented X86 builtin call: ") + + getContext().BuiltinInfo.getName(builtinID)); + return {}; + case X86::BI__builtin_ia32_loadups128_mask: case X86::BI__builtin_ia32_loadups256_mask: case X86::BI__builtin_ia32_loadups512_mask: @@ -1130,6 +1146,8 @@ CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, const CallExpr *expr) { case X86::BI__builtin_ia32_loaddqudi128_mask: case X86::BI__builtin_ia32_loaddqudi256_mask: case X86::BI__builtin_ia32_loaddqudi512_mask: + return emitX86MaskedLoad(builder, ops, getLoc(expr->getExprLoc())); + case X86::BI__builtin_ia32_loadsbf16128_mask: case X86::BI__builtin_ia32_loadsh128_mask: case X86::BI__builtin_ia32_loadss128_mask: diff --git a/clang/test/CIR/CodeGenBuiltins/X86/avx512vl-builtins.c b/clang/test/CIR/CodeGenBuiltins/X86/avx512vl-builtins.c index f03fc75565b1a..da145f0cc4476 100644 --- a/clang/test/CIR/CodeGenBuiltins/X86/avx512vl-builtins.c +++ b/clang/test/CIR/CodeGenBuiltins/X86/avx512vl-builtins.c @@ -363,3 +363,17 @@ __m256i test_mm256_shuffle_i64x2(__m256i a, __m256i b) { // OGCG: shufflevector <4 x i64> %{{.+}}, <4 x i64> %{{.+}}, <4 x i32> <i32 2, i32 3, i32 6, i32 7> return _mm256_shuffle_i64x2(a, b, 0x03); } + +__m128 test_mm_mask_loadu_ps(__m128 __W, __mmask8 __U, void const *__P) { + // CIR-LABEL: _mm_mask_loadu_ps + // CIR: cir.call_llvm_intrinsic "masked.load" %{{.*}}, %{{.*}}, %{{.*}} : (!cir.ptr<!cir.vector<4 x !cir.float>>, !cir.vector<4 x !cir.int<s, 1>>, !cir.vector<4 x !cir.float>) -> !cir.vector<4 x !cir.float> + + // LLVM-LABEL: test_mm_mask_loadu_ps + // LLVM: [[MASK4:%.*]] = shufflevector <8 x i1> %{{.+}}, <8 x i1> %{{.+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + // LLVM: call <4 x float> @llvm.masked.load.v4f32.p0(ptr %{{.+}}, <4 x i1> [[MASK4]], <4 x float> %{{.+}}) + + // OGCG-LABEL: test_mm_mask_loadu_ps + // OGCG: [[MASK4:%.*]] = shufflevector <8 x i1> %{{.+}}, <8 x i1> %{{.+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + // OGCG: call <4 x float> @llvm.masked.load.v4f32.p0(ptr align 1 %{{.+}}, <4 x i1> [[MASK4]], <4 x float> %{{.+}}) + return _mm_mask_loadu_ps(__W, __U, __P); +} _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
