================
@@ -363,3 +363,17 @@ __m256i test_mm256_shuffle_i64x2(__m256i a, __m256i b) {
// OGCG: shufflevector <4 x i64> %{{.+}}, <4 x i64> %{{.+}}, <4 x i32> <i32
2, i32 3, i32 6, i32 7>
return _mm256_shuffle_i64x2(a, b, 0x03);
}
+
+__m128 test_mm_mask_loadu_ps(__m128 __W, __mmask8 __U, void const *__P) {
+ // CIR-LABEL: _mm_mask_loadu_ps
+ // CIR: cir.call_llvm_intrinsic "masked.load" %{{.*}}, %{{.*}}, %{{.*}} :
(!cir.ptr<!cir.vector<4 x !cir.float>>, !cir.vector<4 x !cir.int<s, 1>>,
!cir.vector<4 x !cir.float>) -> !cir.vector<4 x !cir.float>
+
+ // LLVM-LABEL: test_mm_mask_loadu_ps
+ // LLVM: [[MASK4:%.*]] = shufflevector <8 x i1> %{{.+}}, <8 x i1> %{{.+}},
<4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ // LLVM: call <4 x float> @llvm.masked.load.v4f32.p0(ptr %{{.+}}, <4 x i1>
[[MASK4]], <4 x float> %{{.+}})
+
+ // OGCG-LABEL: test_mm_mask_loadu_ps
+ // OGCG: [[MASK4:%.*]] = shufflevector <8 x i1> %{{.+}}, <8 x i1> %{{.+}},
<4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ // OGCG: call <4 x float> @llvm.masked.load.v4f32.p0(ptr align 1 %{{.+}}, <4
x i1> [[MASK4]], <4 x float> %{{.+}})
----------------
andykaylor wrote:
Note the `align` attribute here. We want to match that.
https://github.com/llvm/llvm-project/pull/169464
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