================ @@ -0,0 +1,24 @@ +//===-- RISCVInstrInfoSmip.td ------------------------------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +let mayLoad = 1, Uses = [X2], Defs = [X2, X10, X11, X12, X13, X14, X15], ---------------- zeyi2 wrote:
These effects follow the specified behavior of [mipopret](https://github.com/riscv/riscv-fast-interrupt/blob/6164eca8c8c9138e519ea3b8510655b2b5bb76d0/src/aclic.adoc?plain=1#L2062-L2090) and [sipopret](https://github.com/riscv/riscv-fast-interrupt/blob/6164eca8c8c9138e519ea3b8510655b2b5bb76d0/src/aclic.adoc?plain=1#L2115-L2143): ``` lr a0, OFFSET(sp) # Restore a0 lr a1, OFFSET(sp) # Restore a1 lr a2, OFFSET(sp) # Restore a2 lr a3, OFFSET(sp) # Restore a3 lr a4, OFFSET(sp) # Restore a4 lr a5, OFFSET(sp) # Restore a5 addi sp, sp, FRAMESIZE # Adjust stack pointer scspspop sp, sp # Swap stack pointer with sspcs [m,s]ret ``` The loads require `mayLoad = 1`. `sp` is both read and modified, while `a0–a5` are restored. The final `mret/sret` makes the instruction a return, terminator, and control-flow barrier. https://github.com/llvm/llvm-project/pull/215095 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
