> Hello Declan,
> 
> Will someone with a little testing savvy explain the basics of guarding 
> to me. 
Guarding is shielding with a shield which is actively hold on an 
appropriate voltage. When you have a small differential signal (p.e. 
EEG) with a high common mode voltage, you can give the shield the 
common mode voltage in order not to capacitively load the signal. 
This common mode voltage can be obtained from the instumentation 
amplifier which amplifies the signal. 
So, in my opinion, guarding is not the right answer to your problem.

As for your problem: I suppose you found and used the digital ground 
of the board. Which things fail? Can it be that RESETting the CPU, 
puts the output pins in an open state (3-state outputs?). 
As you say the board is "known to work" what is you aim in testing?
What do you mean with o/ps (outputs?)

Harry


>Let me
> give you an example. This board is populated with 74HC, which is not 
> good stuff to
> short high or low, as it is driven both ways. The databus has eprom, 
> cpu, & 3 support
> chips with /CE going to a 74HC138. That device I desoldered, and the 
> Eprom was pulled,
> to test the support chips.
> /RESET on the cpu is driven from a watchdog chip, via a 74HC4049
> /STDBY is wedded to +5V, and things fail. I grounded the /RESET anyhow 
> and what I'm getting
> is a fail like   "H(or L) expected - Z received" from every output pin. 
> The chips are an 8255 and a 6840.
> Additionally, the 6840 fails an opens test on random pins
> 
> The board is known to work. It has been tested and returned to me.Am I 
> safe pulling 74HC o/ps
> low? High? It's only switched in fior the  functional test, btw, and the 
> devices are not
> continuously powered.
> 
> How does one go about solving this sort of  thing?
> 
>     TIA from the learning curve
> 
>     Declan Moruarty
> 
> -- 
> Author: Declan Moriarty
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> 
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